A5067569047- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- Electromagnetic Compatibility and Noise Suppression
- Cloud Computing and Resource Management
- Caching and Content Delivery
- Electrostatic Discharge in Electronics
- Embedded Systems Design Techniques
- Radiation Effects in Electronics
- Interconnection Networks and Systems
- Physical Unclonable Functions (PUFs) and Hardware Security
- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Advanced Data Storage Technologies
- Power Line Communications and Noise
- Semiconductor materials and devices
- Distributed and Parallel Computing Systems
- Ferroelectric and Negative Capacitance Devices
- Energy Harvesting in Wireless Networks
- VLSI and Analog Circuit Testing
- Optimization and Search Problems
- Advancements in Semiconductor Devices and Circuit Design
- Distributed systems and fault tolerance
University of Cyprus
2015-2020
ARM (United Kingdom)
2015
This paper presents a power delivery monitor (PDM) peripheral integrated in flip-chip packaged 28 nm system-on-chip (SoC) for mobile computing. The PDM is composed entirely of digital standard cells and consists of: 1) fully VCO-based sampling oscilloscope; 2) synthetic current load; 3) an event engine triggering, analysis, debug. Incorporated inside SoC, it enables rapid, automated analysis supply impedance, as well monitoring voltage droop multi-core CPUs running full software workloads...
The current trend for System-on-Chip (SoC) compute subsystems is to improve energy efficiency, while operating at a similar power budget as previous generations. Reduced supply voltages and increased transistor density affords SoCs composed of multiple clusters CPUs additional specialized engines. However, this comes the cost both increasing current, density, extent that these systems are ultimately constrained by delivery. Pathological AC noise conditions may arise due sporadic combinations...
In this paper, we present the results of our comprehensive measurement study timing and voltage guardbands in memories cores a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, reveal how adopted margins vary among 8 CPU chip, 3 different sigma chips show prone they are to worst-case noise. addition, characterize variation 'weak' DRAM cells terms their retention time across 72 evaluate error mitigation efficacy available error-correcting codes case operation under...
The explosive growth of Internet-connected devices will soon result in a flood generated data, which increase the demand for network bandwidth as well compute power to process data. Consequently, there is need more energy efficient servers empower traditional centralized Cloud data-centers emerging decentralized at Edges Cloud. In this paper, we present our approach, aims developing new class micro-servers - UniServer that exceed conservative and performance scaling boundaries by introducing...
This work presents GeST (Generator for Stress-Tests): a framework automatically generating CPU stress-tests. The is based on genetic algorithm search and can be used to maximize different target metrics such as power, temperature, instructions executed per cycle dl/dt voltage noise. We demonstrate the generality effectiveness of by various workloads that stress thermal margins more than both conventional benchmarks manually written key strengths are its extensibility flexibility. user...
This work proposes sensing CPU voltage noise through wireless electromagnetic (EM) emanations from the CPU. Compared to previous monitoring methodologies, this approach is not intrusive as it does require direct physical access monitored To prove effectiveness of approach, we use EM signal feedback find resonant frequency power delivery network, and generate a (dI/dt) virus. study performed on modern out-of-order that supports on-chip fine grain monitoring. capability used validate proposed...
Worst-case dI/dt voltage noise is typically characterized post-silicon using direct measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources suffer from design-time and run-time overheads. This work proposes an alternative non-intrusive, zero-overhead approach for generation based on sensing CPU electromagnetic emanations antenna a spectrum analyzer. The the observation that high amplitude are correlated with...
This work performs a thorough characterization and analysis of the open source Lucene search library. The article describes in detail architecture, functionality, micro-architectural behavior engine, investigates prominent online document research issues. In particular, we study how intra-server index partitioning affects response time throughput, explore potential use low power servers for search, examine sources performance degradation ands causes tail latencies. Some our main conclusions...
Web search as a service is very impressive. runs on thousands of servers which perform an index billions web pages. The results must be both relevant to the user queries and reach in fraction second. A guarantee same QoS at all times even peak incoming traffic load. Not unjustifiably has attracted lot research attention. Despite high interest gained, there are still plenty unknown about functionality architecture benchmarks. Much been done using commercial engines, like Bing or Google, but...
Worst-case dI/dt voltage noise is typically characterized post-silicon using direct measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad resources suffer from design-time and run-time overheads. This work proposes an alternative non-intrusive, zero-overhead approach for characterization based on sensing CPU electromagnetic emanations antenna a spectrum analyzer. the observation that high amplitude are correlated with...
The common practice for quantifying the benefit(s) of design-time architectural choices server processors is often limited to chip- or server-level. This quantification process invariably entails use salient metrics, such as performance, power, and reliability, which capture-in a tangible manner-a designs overall ramifications. paper argues necessity more holistic evaluation approach, considers metrics across multiple integration levels (chip, datacenter). In order facilitate said...
Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry an everlasting scaling of devices in silicon. Nevertheless, integration miniaturization transistors comes with important non-negligible trade-off: time-zero time-dependent performance variability. Increasing guard-bands to battle variability is not scalable, since worst-case design margins prohibitive for downscaled technology nodes. This...
This work reports on the results of a performance characterization Simultaneous Multi-Threading (SMT) and Index-Partitioning (IP) when executing an online document search application. One key paper findings is that SMT suitable for latency sensitive In particular, our analysis shows while degrades single-thread execution latency, it still improves overall response-latency (queueing plus latency) because multiple contexts increase available throughput help decrease sufficiently queuing...