Echocardiography is a commonly used and cost-effective test to assess heart conditions. During the test, cardiologists technicians observe two cardiac phases-end-systolic (ES) end-diastolic (ED)-which are critical for calculating chamber size ejection fraction. However, non-essential frames called Non-ESED may appear between these phases. Currently, or manually detect phases, which time-consuming prone errors. To address this, an automated efficient technique needed accurately phases...

ABSTRACT An important problem in teaching the subjects of Computer Architecture and Organization (CO&CA) is linking theoretical knowledge with practical experience. Visualization different computer hardware architectures use simulators enhances learning process among students. Many useful can help address this issue by covering various aspects CO&CA. The programs range from simple to specific tools advanced specialized software. We assessed several selected one that was freely...

Recently, the telecommunication standard development body reported LTE support for V2X services-based use cases along with their potential requirements. However, these requirements overlap and require a huge effort to understand. Therefore, it is imperative know outcomes of categorization In this paper, we provided an overview cases, outcomes, comparison between based on i.e. latency, message size, mobility performance, response time, frequency, anonymity integrity, reliability,...

This work investigates issues and challenges of cyber security, specifically malware targeting mobile devices. Recent advances in technology have provided high CPU power, large storage, broad bandwidth integrated peripheral devices such as Bluetooth, Wi-Fi, 3G/4G to devices, making them popular computing communication Mobile has been more than ever seems be shifted from their traditional host, the personal computers, vulnerable victims. In this study, we mainly focus on for Android-based We...

Gastric cancer is the fourth most commonly diagnosed malignancy and second leading cause of cancer-related mortality worldwide. Recent research suggests that tissue stem cells self renewal transcription factor, octamer-binding factor 4 (Oct4), could be involved in development certain tumors. The aim this study was to investigate expression pattern Oct4 normal human stomach during multistep gastric carcinogenesis. Pyloric antral mucosal tissues were obtained from consenting individuals...

Generic as well customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate of both present future (nano)circuits. However, accuracy many these EDA is questionable they: 1) either assume that all gates same constant probability failure ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PF</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> =...

Introducing redundancy at the device-level has been proposed as most effective way to improve reliability. With remarkable reliability of complementary metal oxide semiconductor (CMOS) transistors industry was able fabricate, research on reduced. However, increasing sensitivity noise and variations (due massive scaling) CMOS led a revival interest in schemes during last decade. In this paper, we introduce novel transistor sizing method that can be used significantly reduce probability...

Left ventricular hypertrophy (LVH) is a life-threatening condition in which the muscle of left ventricle thickens and enlarges. Echocardiography test performed by cardiologists echocardiographers to diagnose this condition. The manual interpretation echocardiography tests time-consuming prone errors. To address issue, we have developed an automated LVH diagnosis technique using deep learning. However, availability medical data significant challenge due varying industry standards, privacy...

This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating at low voltages. The relies on upsizing the length (L) of all transistors uniformly, balancing voltage transfer curves (VTCs) maximizing static noise margins (SNMs). We use most well-known (INV, NAND-2, NOR-2) introducing novel method, as well validating concept evaluating its performances. results show that has not entirely exhausted potential, allowing to go beyond...

Reducing the supply voltage is by far most widely used low-power technique, as reducing dynamic power quadratically and leakage linearly, while sacrificing on performances. A similar but less explored route to reduce and/or limit currents (instead of voltages), e.g., through transistor sizing. This paper details a comparison reverse-sized CMOS scheme (which reduces currents), with both classical implementation an ultra low (ULP) sub-threshold scheme. Simulation results show that inverter...

Full adders (FAs) are essential for digital circuits including microprocessors, signal processors, and microcontrollers. Both the power consumption reliability of FAs crucial as they directly affect: arithmetic logic units, floating-point well memory address calculations. This paper studies effect threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) variations play on a classical 28-transistor FA, shows that can be...

Summary This paper presents an automatic method for sizing the transistors in CMOS gates. The utilizes a feedback control system to efficiently optimize transistor sizes small and large fan‐in gates, with primary goal of enhancing noise robustness (as characterized by static margin). gates retain their under threshold‐voltage variations over range supply voltages. optimized not only expend reduced power energy, but also take up less area than conventional ones. These multi‐faceted gains,...

Abstract This paper presents a Web‐based tool for predicting the performance of computer systems. The can be used teaching how hardware configurations (processor microarchitecture, memory hierarchy, etc.) and/or software (benchmark program) characteristics affect system throughput. Use proposed in architecture classes has demonstrated its effectiveness improving students' understanding related topics. © 2009 Wiley Periodicals, Inc. Comput Appl Eng Educ 17: 305–313, 2009; Published online...

ABSTRACT The characterization of standard cells (basic digital blocks) is an iterative and arduous process. Our web‐based tool enables the students/users to quickly perform a large number experiments. useful for various courses on micro/nano‐electronics circuit design, eliminates need costly CAD‐software/hardware. © 2014 Wiley Periodicals, Inc. Comput Appl Eng Educ 23:304–313, 2015; View this article online at wileyonlinelibrary.com/journal/cae ; DOI 10.1002/cae.21600

Digital logic design is an essential topic in the computer science curriculum. A major challenge teaching to have students connect their theoretical knowledge with practical experience. Many useful programs are available that can help overcome this issue while covering various aspects of design. The range from simple simulators advanced and specialized software. This paper presents our experience selecting incorporating a few simulation tools for improvement results course final examinations...

Integrated circuits in the coming years are expected to be based on nano-scaled devices, such as single electron transistors, self-assembled DNA, carbon nano-tubes, and resonant tunnel diodes. Future designs nano-devices will exhibit high integration densities, might either low power or fast switching but not both. Unfortunately, suffer heavily from fabrication inconsistencies, transient permanent failures due external causes. Therefore, circuit reliability have added design space currently...

The minimization of logic gates is needed to simplify the hardware design area programmable arrays (PLAs) and speed up circuits. VLSI designers can use methods produce high speed, inexpensive energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) an attractive algorithm for simplifying Boolean expressions because it handle any number variables. This paper describes a new model estimation circuit complexity, based on simplification method. proposed method...

Voltage controller oscillator (VCO) based CMOS temperature sensors are capable of lower power operation (albeit at the cost sensitivity and resolution) than their BJT counterparts. The consumption sense conversion blocks is much VCO itself hence any further reduction would be a daunting task. In this work, we compare performance three types VCOs that suitable for ultra-low sensing. proposed have been implemented in 150 nm standard technology, biased sub-threshold region to ensure operation....

The unrelenting scaling of CMOS devices has brought their dimensions down to few tens nanometers. In such sizes, the reliability margins drop ominously and leakage power dissipation increases significantly. This paper presents a non-conventional transistor-sizing method for improving by increasing static noise margin, while simultaneously reducing consumption. Simulations results have been used compare consumption, performance classical gates with proposed scheme in 22 nm technology. show...

Making the students understand theoretical concepts of digital logic design is one major issues faced by academics, therefore teachers have tried different techniques to link information practical knowledge. Use software simulations a technique for learning and practice that can be applied many disciplines. Experimentation computer hardware components/integrated circuits with use simulators enhances student learning. The rather simplistic or quite complex. This paper reports our evaluation...

Being able to model the complexity of Boolean functions in terms number nodes a binary decision diagram can be quite useful VLSI/CAD applications. Our investigation showed that it is possible use recurrent neural network (RNN) models for prediction circuit complexity. The modeling results matched closely with simulations an average error less than 1 %. correlation coefficient between RNN's predictions and actual ISCAS benchmark circuits was 0.629.