The physical unclonable function (PUF) serves as a security primitive of circuits, which is applicable to the embedded systems with lightweight authentication function. However, modeling attack, estimates unknown CRPs by establishing mathematical model PUF, real threat PUF based crypto-systems. Subsequently, anti-modeling-attack becomes research hotspot. systematic design method secure still open issue, although some schemes have been proposed on repeated trials. This work proposes...

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, closely clustered TSVs suffer from crosstalk noise between neighboring TSVs, and result extra delay deterioration of signal integrity. For a 3 × TSV array, severity center victim is classified into 11 levels, which defined 0C to 10C low high noise, depending on combinations digital patterns applied array. An enhanced code based Fibonacci number system (FNS)...

This paper presents a new method of human motion recognition based on MEMS inertial sensors data. A Micro Inertial Measurement Unit (μIMU) that is 56mm*23mm*15mm in size was built. unit consists three dimensional accelerometers, gyroscopes, Bluetooth module and MCU (Micro Controller Unit), which can record transfer data to computer through serial port wirelessly. Five categories were done including walking, running, going upstairs, fall standing. Fourier analysis used extract the feature...

The single event upset (SEU) in integrated circuit (IC) occurs due to the striking of heavy charged particles. It results multiple node (MNU) problem frequently, with scaling down semiconductor devices. To address this challenge, radiation hardening by design (RHBD) methods are required, addition layout and device level techniques. latch is one basic components logic circuit, RHBD method still an open issue. Muller C-element (MCE) and/or dual interlocked storage cell (DICE) based for...

For the tri-layer symmetric magnetoelectric (ME) laminates made of giant magnetostrictive materials and piezoelectric materials, we established a theoretical model for nonlinear thermo-magneto-electric coupling effect in laminates. This was calculated an iterative approach. It adopted magneto-thermo-mechanical constitutive linear mechanical-thermo-electric introduced interface factor to describe strain transfer efficiency between layers. The predictions ME coefficient versus temperature...

In conventional HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based resistive random access memory (RRAM), SiO is usually adopted as side wall spacer (low-k spacer) to define the device feature size. It found that forming voltage of RRAM with rises when size scaling down from 16.0 μm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 0.16 , which detrimental for application high density RRAM. this study, a permittivity...

High Efficient Video Coding (HEVC) is the latest coding standard with superior compression efficiency while its encoding complexity much higher compared H.264/AVC. Motion estimation one of most time-consuming parts in video coding. In reference software HEVC, TZ (Test Zone) search method adopted as fast motion method. However, still high. There are many other methods, for example, hexagon method, but their performance loss larger than search. order to balance speed and performance, a new...

An improved fast acquisition phase-frequency detector (PFD) for Phase-Locked Loop (PLL) is presented. The proposed PFD completely eliminates the blind zone, which caused by missing input edge during reset pulse. It has a linear output range and saturated when phase error in [0, π] [π, 2π]. simulation results with SMIC 65nm CMOS technology file show that, comparing published works, nonlinear gain faster lock process, improves maximum operating frequency to as higher 1GHz.

Two hybrid memristor-MOS exclusive OR (XOR) and NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed present states with voltages, implement the operation within one clock cycle. designs ease voltage degradation problem of original MRL gates, while consuming fewer area overhead less delay than their counterparts.

A SPICE model for phase change memories (PCM) without relying on macro modules is developed in this work. The crystal fraction, physical geometry, and the conduction path of amorphous region are treated as dynamic state variables to keep track memory cell status during SET RESET. resistance calculated based a detail 3-D capture its transitional behavior switching. formulation correctly reproduced recent observation oscillation operation. has been implemented SPICE, convergence demonstrated...

In this paper, we present a new method to calibrate the misalignment error and zero offset of MEMS accelerometer, which applies Genetic Algorithm (GA) process measured data get model parameters. This can effectively eliminate caused by assembly deviation between sensitive sensor unit package shell. Results show that calibrated output is far more accurate than raw obtained only used factory calibration. The mean squared (MSE) before calibration 1.754×10 <sup...

An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of linear-feedback-shift-register (LFSR)- based pattern generator and multi-input signature register (MISR)-based response compactor, both n-stage LFSR MISR are implemented by n + 2 RRAM cells. LFSR/MISR has better performance than IMPLY-based counterpart, due to application three-cycle XOR gate two-cycle shift with And it more area efficient...

Elliptic curve cryptography (ECC) is one of the most popular public key cryptosystems in recent years due to its higher security strength and lower resource consumption. However, noninvasive side-channel attacks (SCAs) have been proved be a big threat ECC systems many previous researches. In this paper, we propose low-area-time-product coprocessor for GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) with ability resist existing...

Polymorphic gates are reconfigurable devices whose functionality may vary in response to the change of execution environment such as temperature, supply voltage or external control signals. This feature makes them a perfect candidate for circuit watermarking. However, polymorphic hard find because they do not exhibit traditional structure. In this paper, we report four dual-function that have discovered using an evolutionary approach. With these gates, propose watermarking scheme selectively...

March W-1T1R, a high fault coverage test, is proposed to cover not only the tranditional set, but also newly discovered write disturbance (WDF) and dynamic (dWDF) in 1T1R memristor arrays. The analysis shows that W-1T1R algorithm with complexity of 17N, where N number memory cells array, enhances little time increasement, comparing previous algorithms.

Graphics rendering is a compute-intensive work and major source of energy consumption on battery-driven mobile devices. Unlike the existing works that degrade user experience or reuse results coarsely, we propose ReTriple, fine-grained scheme to reduce workload by reusing past at UI element level. This mechanism can explore more opportunities process save energy. The experiments tested with popular apps show ReTriple achieves an average speedup 2.6x per-frame saving 32.3% for while improving...

The polymorphic gates are the circuit cells that deliver different functions with external input, supply voltage or temperature. It is an effective method to resist reverse engineering attacks, for attackers cannot distinguish correct function based on netlist of circuit. researchers have found out RRAM Look-Up Table (LUT) has higher performance and less area, comparing CMOS counterparts. However, can tell previous proposed LUTs by measuring resistance states cells. This work proposes gate,...

The iMemComp (Intelligent memristive computing) gates are a family of logic based on the RRAM (Resistive Random Access Memory) devices. It has potential advantage for design high-performance circuits, because NAND, AND, NOT, and transmission only consume single cycle, respectively. However, original two-input OR gate, which requires three cycles, is relatively slow gate. decreases performance some circuits. This work proposes an improved gate with one cycle cells. Both circuit area...

The synthesis method of logic circuits based on the RRAM (Resistive Random Access Memory) devices is great concern in recent years. Inspired by CMOS-like gates, this work proposes a NMOS-like gate family. advantages proposed gates include: (1) all are array-implementable; (2) family complete; (3) NOR, AND and NOT only consume single cycle respectively computation phase; (4) save half number compared with counterparts. Furthermore, discussed. single-cycle utilized priority under constraints...