As a strong candidate for future electronics, atomically thin black phosphorus (BP) has attracted great attention in recent years because of its tunable bandgap and high carrier mobility. Here, we show that the transport properties BP device under electric field can be improved greatly by interface engineering high-quality HfLaO dielectrics orientation. By designing channels along lower effective mass armchair direction, record-high drive current up to 1.2 mA/μm at 300 K 1.6 20 achieved...

In this paper, hot carrier degradation (HCD) in FinFET is studied for the first time from trap-based approach rather than conventional carrier-based approach, with full Vgs/Vds bias characterization and self-heating correction. New HCD dependence observed, which cannot be predicted by traditional models. A compact model proposed verified both n- p-type FinFETs, unified across different regions transport mechanisms. Impacts of on analog circuits also demonstrated, showing runaway effect. The...

In this brief, typical locations of the interface and oxide traps generated by hot carrier degradation (HCD) in FinFETs are studied with experiments “atomistic” TCAD simulations under worst case stress conditions. The round-Fin different types analyzed comparing experimentally extracted results calibrated simulations. Then, traps' impacts on HCD variations both forward reverse bias modes employed to disclose lateral traps. suggest that for n- p-type conditions, (type 1) mainly distributed...

In this paper, the recent advances of our studies on hot carrier degradation (HCD) are presented from trap-based approach. The microscopic speculation interface trap generation is carried out by time-dependent DFT (TDDFT) simulation in "real-time". Two types oxide traps contributing to HCD identified experiments. Combining contributions and traps, a unified compact model has been proposed which can accurately predict variation full <tex xmlns:mml="http://www.w3.org/1998/Math/MathML"...

In this paper, an industry-level new-generation EDA solution for reliability-aware design in nanoscale FinFET technology is presented the first time, with new compact transistor aging models and upgraded circuit reliability simulator. Our work solves various issues found silicon data of NBTI aging. Especially, instead ignoring or less accurate recovery effect model traditional simulators, degradation are proposed validated by full stress/recovery range technology. The history effect, one...

Device variability and reliability are becoming increasingly important for nano-CMOS technology circuits, due to the shrinking circuit design margin with downscaling supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ). Therefore, robust should have awareness of both reliability. In FinFET technology, strong correlation between variations device electrical parameters is found, larger impacts line-edge roughness (LER) in...

In this article, the dynamic variability induced by hot carrier degradation (HCD) in FinFETs is studied with decomposing variation contributions of multiple types traps. The nonlinear relationship μ-σ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (ΔVth) are newly observed both n- and p-type FinFETs. A multi-trap-based HCD model proposed verified impacts variations on static random-access memory (SRAM) read/write stability also...

In this letter, the lateral trap distributions in planar and FinFET devices are experimentally studied under various bias stress conditions of hot-carrier degradation (HCD). contrast to traditional understanding that generated traps crowded near drain region during stress, it is found peak distribution profile will gradually move closer source with increase V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> stress. The results suggest...

The temperature dependence of hot carrier degradation (HCD) in FinFET is observed to vary with bias conditions, channel local and time. It found that the total HCD consist both contributions from interface traps oxide traps, whose individual behaviors are different. Therefore, composition varies different conditions causing nonuniversal HCD. understandings helpful for physical investigation modeling advanced Technology.

In this paper, the statistical characteristics of complex RTN (both DC and AC) are experimentally studied for first time, rather than limited case-by-case studies. It is found that, over 50% RTN-states predicted by conventional theory lost in actual statistics. Based on mechanisms non-negligible trap interactions, new models proposed, which successfully interpret state-loss behavior, as well different SiON high-κ devices. The circuit-level study also indicates predicting circuit stability...

We extend our compact physics model for hot-carrier degradation (HCD) by implementing the contribution to damage caused secondary carriers (generated impact ionization) and revisiting transport modeling primary carriers. To verify we employ planar field-effect transistors (FETs) with a gate length of 28 nm, which were subjected HC stress under <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{gs}}=V_{\text{ds}}(V_{\text{gs}}$</tex> ,...

In this paper, an industry-level new-generation EDA solution for reliability-aware design in nanoscale FinFET technology is presented the first time, with new compact transistor aging models and upgraded circuit reliability simulator. Our work solves various issues found silicon data of NBTI aging. Especially, instead ignoring or less accurate recovery effect model traditional simulators, degradation are proposed validated by full stress/recovery range technology. The history effect, one...

In this paper, it is reported for the first time that, in nanoscale high-k/metal-gate MOSFETs, hot carrier degradation (HCD) follows a two-stage law some stress conditions. Both interface traps and oxide contribute to HCD causing its time-dependence varies with different modes. The results are helpful physical understanding of devices.

In this paper, our recent studies on the hot carrier degradation (HCD) in FinFETs, as well HCD-induced dynamic variability, are summarized. The kinetics and statistics of FinFET HCD experimentally investigated. New observations reported, which due to simultaneous generation both interface oxide traps. Based trap-based approach, instead conventional carrier-based its variations well-described with proposed multi compact models, that unified over full {Vgs,Vds} bias region. typical average...

In this paper, the impact of body bias on hot carrier degradation (HCD) in advanced FinFET devices is experimentally investigated. It observed that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dsat</sub> increasing with for short-channel core devices, while an opposite tendency found long-channel IO devices. The different dependences are due to mechanisms single-carrier event (SCE) but multi-carrier (MVE) results helpful physical understanding HCD

In this paper, a new method named Incremental Trap-Response (ITR) is proposed for characterizing the time constants of switching oxide traps, which can be used to expand voltage detectable window RTN. Both theoretical and experimental results demonstrate that ITR has higher accuracy more time-efficient than recently Statistical (STR) method, thus helpful trap-related research on both reliability variability.

In this paper, the degradation of drain-induced barrier lowering (DIBL) in FinFETs is experimentally studied under various hot carrier (HCD) stress conditions. A test method developed to characterize channel height modulation different HCD linear relationship ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">thlin</sub> and xmlns:xlink="http://www.w3.org/1999/xlink">thsat</sub> after found. Then a compact model HCD-induced ΔDIBL proposed. The...

We develop a compact physics model for hot-carrier degradation (HCD) that is valid over wide range of gate and drain voltages (Vgs Vds, respectively). Special attention paid to the contribution secondary carriers (generated by impact ionization) HCD, which was shown be significant under stress conditions with low Vgs relatively high Vds. Implementation this based on refined modeling carrier transport both primary carriers. To validate model, we employ foundry-quality n-channel transistors...

HCI degradation of pass-gate transistor with forward and reverse stress biases in advanced FinFET technology is investigated comprehensively. Due to the bidirectional stress, shows larger than conventional HCI, which can induce up 50% error predicting delay degradation. Based on proposed underlying physics, compact model developed verified. With further analysis circuit level, new simulation methodology demonstrated. It thus helpful reliability-aware design technology.

In this paper, the recent advances of our studies on hot carrier degradation (HCD) are presented from trap-based approach. The microscopic speculation interface trap generation is carried out by time-dependent DFT (TDDFT) simulation in "real-time". Two types oxide traps contributing to HCD identified experiments. Combining contributions and traps, a unified compact model has been proposed which can accurately predict variation full Vgs/Vds bias. locations, temperature dependence studied...