A5044344679- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Neural dynamics and brain function
- Neural Networks and Reservoir Computing
- Neuroscience and Neural Engineering
- CCD and CMOS Imaging Sensors
- Neural Networks and Applications
- Photoreceptor and optogenetics research
- Molecular Communication and Nanonetworks
- Computational Physics and Python Applications
- Modular Robots and Swarm Intelligence
- Advancements in PLL and VCO Technologies
- Semiconductor Lasers and Optical Devices
- Flexible and Reconfigurable Manufacturing Systems
- 3D IC and TSV technologies
- Interconnection Networks and Systems
- Analog and Mixed-Signal Circuit Design
Heidelberg University
2012-2024
Kirchhoff (Germany)
2011-2024
Instituto Valenciano de la Edificación
2023
Institute for Physics
2017-2020
Heidelberg University
2006-2017
Significance Neuromorphic systems aim to accomplish efficient computation in electronics by mirroring neurobiological principles. Taking advantage of neuromorphic technologies requires effective learning algorithms capable instantiating high-performing neural networks, while also dealing with inevitable manufacturing variations individual components, such as memristors or analog neurons. We present a framework resulting bioinspired spiking networks high performance, low inference latency,...
In this study, we present a highly configurable neuromorphic computing substrate and use it for emulating several types of neural networks. At the heart system lies mixed-signal chip, with analog implementations neurons synapses digital transmission action potentials. Major advantages emulation device, which has been explicitly designed as universal network emulator, are its inherent parallelism high acceleration factor compared to conventional computers. Its configurability allows...
Emulating spiking neural networks on analog neuromorphic hardware offers several advantages over simulating them conventional computers, particularly in terms of speed and energy consumption. However, this usually comes at the cost reduced control dynamics emulated networks. In paper, we demonstrate how iterative training a hardware-emulated network can compensate for anomalies induced by substrate. We first convert deep trained software to BrainScaleS wafer-scale system, thereby enabling an...
Neuromorphic devices represent an attempt to mimic aspects of the brain's architecture and dynamics with aim replicating its hallmark functional capabilities in terms computational power, robust learning energy efficiency. We employ a single-chip prototype BrainScaleS 2 neuromorphic system implement proof-of-concept demonstration reward-modulated spike-timing-dependent plasticity spiking network that learns play simplified version Pong video game by smooth pursuit. This combines electronic...
We present results from a new approach to learning and plasticity in neuromorphic hardware systems: enable flexibility implementable mechanisms while keeping high efficiency associated with implementations, we combine general-purpose processor full-custom analog elements. This is operating parallel fully system consisting of an array synapses connected analog, continuous time neuron circuits. Novel correlation sensor circuits process spike events for each synapse real-time. The uses this...
This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI model spiking neural network. The artificial synapses are based on spike time dependent (STDP). In the biological specimen, STDP is mechanism acting locally each synapse. presented electronic succeeds maintaining this high level parallelism and simultaneously achieves synapse density more than 9k per mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal is embedded in analog network core a scaled-down prototype high input count neural with digital learning system chip. Designed as continuous-time circuits, neurons are highly tunable and reconfigurable elements accelerated dynamics. Each integrates current from multitude incoming synapses evokes spike event output....
This demonstration is based on the wafer-scale neuromophic system presented in previous papers by Schemmel et. al. (20120), Scholze (2011) and Millner (2010). The setup will allow visitors to monitor partially manipulate neural events at every level. They get an insight into complex interplay between packet-based realtime communication necessary combine continuous-time mixed-signal networks with a transport network. Several network experiments implemented be accessible for user interaction.
Here, we describe a multicompartment neuron circuit based on the adaptive-exponential I&F (AdEx) model, developed for second-generation BrainScaleS hardware. Based an existing modular leaky integrate-and-fire (LIF) architecture designed in 65-nm CMOS, features exponential spike generation, neuronal adaptation, intercompartmental connections as well conductance-based reset. The design reproduces diverse set of firing patterns observed cortical pyramidal neurons. Further, it enables emulation...
We present first experimental results on the novel BrainScaleS-2 neuromorphic architecture based an analog neuro-synaptic core and augmented by embedded microprocessors for complex plasticity experiment control. The high acceleration factor of 1000 compared to biological dynamics enables execution computationally expensive tasks, allowing fast emulation long-duration experiments or rapid iteration over many consecutive trials. flexibility our is demonstrated in a suite five distinct...
The massively parallel nature of biological information processing plays an important role due to its superiority in comparison human-engineered computing devices. In particular, it may hold the key overcoming von Neumann bottleneck that limits contemporary computer architectures. Physical-model neuromorphic devices seek replicate not only this inherent parallelism, but also aspects microscopic dynamics analog circuits emulating neurons and synapses. However, these machines require network...
Abstract This paper presents verification and implementation methods that have been developed for the design of BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits two general purpose microprocessors (PPU) SIMD extension on-chip learning plasticity. Simulation automated analysis pre-tapeout calibration highly parameterizable neuron synapse hardware-software co-development digital logic...
High-level brain function such as memory, classification or reasoning can be realized by means of recurrent networks simplified model neurons. Analog neuromorphic hardware constitutes a fast and energy efficient substrate for the implementation neural computing architectures in technical applications neuroscientific research. The functional performance is often critically dependent on level correlations activity. In finite networks, are typically inevitable due to shared presynaptic input....
Despite being originally inspired by the central nervous system, artificial neural networks have diverged from their biological archetypes as they been remodeled to fit particular tasks. In this paper, we review several possibilites reverse map these architectures biologically more realistic spiking with aim of emulating them on fast, low-power neuromorphic hardware. Since many devices employ analog components, which cannot be perfectly controlled, finding ways compensate for resulting...
BrainScaleS-1 is a wafer-scale mixed-signal accelerated neuromorphic system targeted for research in the fields of computational neuroscience and beyond-von-Neumann computing. The BrainScaleS Operating System (BrainScaleS OS) software stack giving users possibility to emulate networks described high-level network description language PyNN with minimal knowledge system. At same time, expert usage facilitated by allowing hook into at any depth stack. We present operation development...
Together with the Kirchhoff-Institute for Physics Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base large-scale neuromorphic hardware system. The paper will give an overview of computing platform at associated requirements which drove described technological developments. In first phase project standard technologies from level packaging were adapted to enable high density reticle-to-reticle routing on 200 mm CMOS wafers. Neighboring reticles...