Task scheduling and core mapping have a significant impact on the overall performance of network chip (NOC). In this paper, unified task algorithm called UNISM is proposed for different NOC architectures including regular mesh, irregular mesh custom networks. First, model combining introduced using mixed integer linear programming (MILP). Then, novel graph to consider irregularity estimate communication energy latency, since number hops not accurate enough To make MILP-based scalable,...

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, hierarchical flow inter-layer partitioning method. The blocks partitioned into different layers before floorplanning. A simulated annealing (SA) engine used partition the...

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the resistances between device layers. In this paper, we integrate dynamic via planning floorplanning process. Our and approaches are implemented in two-stage approach. Before floorplanning, temperature-constrained vertical formulated as convex programming problem. Based on analytical solution, blocks assigned different layers solving sequence of knapsack problems. Then SA engine used...

In this paper, we investigate thermal via (T-via) planning during three-dimensional (3-D) floorplanning. First, consider the temperature constrained T-via (TVP) problem on a given 3-D floorplan. Second, integrate dynamic TVP into floorplanning process. Our main contribution and results can be summarized as follows. We solve by solving sequence of simplified interlayer intralayer subproblems. Each subproblem is formulated convex programming derive nearly optimal solution for detailed...

Fixed-outline floorplanning, which enables hierarchical design, is considered more and important nowadays. In this paper, a novel SA-based Floorplanner with the Optimal Area utilization named SAFFOA introduced to improve total wirelength. The basic idea build solve group of four quadratic equations in variables iteratively, can handle fixed-outline constraint any aspect ratio. A new topological representation called Ordered Quadtree then custom-made for facilitate its integration into SA...

In this paper we propose a novel binding mechanism that can protect FPGA IP from being cloned, tampered, or misused; and facilitate the pay-per-use licensing to limit IP's execution specific devices only. mechanism, vendors will provide each enrolled device with Physical Unclonable Function (PUF) be deployed securely during fabrication process. The core vendor embed an augmented Finite State Machine (FSM) into original FSM structure of hardware (HW-IP) react on PUF response given challenge....

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven algorithm with power distribution constraints; (3) considering congestion minimization. Experiments results show that our approach is nine times faster better quality...

Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools current DPR design flow, leveraging these requires specific designer expertise with laborious manual effort. Considering complicated concurrency relations among functions, is challenging properly select Modules (PR Modules) partition them into groups so...

Power gating is one of the most effective techniques for low power design because it reduces both dynamic and static simultaneously. This paper proposes a circuit architecture to implement in sequential circuits based on finite state machine (FSM) decomposition, which implemented by partition transition graph (STG). The FSM partitioned into two or more sub-machines, only active time, supply other sub-machines can be cut off save energy. Since adjustment voltage may not finish instantly,...

Constrained random stimulus generation plays significant roles in hardware verification nowadays, and the quality of generated stimuli is key to efficiency test process. In this work, we present a linear dynamic method guide by SAT solvers. A splitting simplified Min-Distance-Sum evaluation an XOR sampling strategy are integrated self-adjusting framework. The evenness split groups evaluated find out some uneven parts. Then, partial solutions for parts constraints other inputs added into get...

A hierarchical CDFG model designed as an intermediate representation for hardware/software (HW/SW) codesign is presented in this paper. new concept of transport node, which represents the communication resources system, proposed model. Hierarchical feature can be straightly obtained through extending definition nodes, allowing them to nest sub-CDFG recursively. Then it demonstrated how build basic control constructs branches and loops. Explaining a short introduction translation process,...

This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is extended Davis-Putnam-Logemann-Loveland procedure (DPLL) which unified combining Boolean logic and arithmetic operations. A two-literal-watching scheme interval reasoning based on predicates are used as powerful constraint propagation strategies. Conflict-based learning also implemented...

High temperature adversely impacts on reliability, performance, and leakage power of ICs. In behavioral synthesis, both resource usage allocation binding influence the final thermal profile. Previous thermal-aware syntheses only focused binding, ignoring allocation. This paper proposes synthesis with According to density feedbacks from simulation, we allocate number resources under area constraint. Our flow effectively controls peak creates even densities among “different” “same” types....

Constrained random stimulus generation plays significant roles in hardware verification nowadays, and the quality of generated stimuli is key to efficiency test process. In this work, we present a linear dynamic method guide by SAT solvers. A splitting simplified Min-Distance-Sum evaluation an XOR sampling strategy are integrated self-adjusting framework. The evenness split groups evaluated find out some uneven parts. Then, partial solutions for parts constraints other inputs added into get...

To further exploit the potential of reconfigurable computing, fine-grain, super massive parallel processing SAT solver over hardware accelerator is proposed in this paper as SMPP. By analyzing traditional solver, we a novel way to partition original problem into software part and part. Software uses semi-confliction guided backtrack extract equivalent fixed scale sub-problem sequence. Partition scheme SMPP exploited stage effect inference engine modern solver. Hardware tiny cells handle...

As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing routing vias will facilitate the lithography and give higher yield also performance. In this paper, we present floorplan revising method to minimize number of reducible with controllable loss on area wirelength. Therefore, it easy make proper tradeoff between via reduction loss. Experiments show that our reaches 96.2% 93.5% vias, which close 100% runs fast. Besides, friendly all...

This paper presents a low frequency architecture for driving parallel cold cathode fluorescent lamps (CCFLs) in large screen LCD TV backlighting applications. Key to the is proposed capacitive coupling approach AC lamp ignition. The system consists of single high voltage converter, an ignition circuit, current regulation devices and primary controller. topology capable arbitrary number with independent accurate regulation, while maintaining efficiency achieving significant size, weight, cost...

As the dimension of integrated circuits proceeds into deep sub-micron level, interconnect delay is playing a dominant role in total circuit. The result high-level synthesis often violated by interconnect-delay physical design phase, especially timing aspect. Reallocation and Rescheduling after floor-plan can be very helpful to optimization design. A force-balance based driven algorithm for reallocation rescheduling (FIDER) presented this paper. wire specially attended algorithm. In...

To improve the observability during post-silicon validation, it is key to select limited trace signals effectively for data acquisition. This paper proposes an automated signal selection algorithm, which uses pruning-based strategy reduce exploration space. First, restoration range covered each candidate signals. Second, constraints are generated based on conjunctive normal form (CNF) avoid conflict. Finally candidates selected through enumeration. The experimental results indicate that...

Control and Data Flow Graph (CDFG) is a universal description of program behavior, which widely used in the co-design software hardware. The derivation CDFG has been done mostly by manually or automatically analyzing corresponding source code, makes this process time-consuming, error-prone incomplete. In paper, we proposed an automated design flow based on runtime instrumentation to generate Enhanced (ECDFG) with additional information. Though approach debugging analyze accurate information,...

With the development of VLSI, embedded system is growing sharply. A new methodology, Co-design, appeared to meet needs designing. System designers require good EDA tools, which support Co-design methodology. Debug an important part design process, so we improved a debug subsystem fit Co-design. Different from traditional software was designed reflect real and comprehensive status system. To achieve this goal, add little circuit original The will control collect information that designer...

Article Free Access Share on IBAW: an implication-tree based alternative-wiring logic transformation algorithm Authors: Wangning Long Dept. Computer Sci. & Tech., Tsinghua University, Beijing, 100084, China ChinaView Profile , Yu-Liang Wu Eng., The Chinese University of HK, Shatin, NT, Hong kong kongView Jinian Bian Authors Info Claims ASP-DAC '00: Proceedings the 2000 Asia and South Pacific Design Automation ConferenceJanuary Pages 415–422https://doi.org/10.1145/368434.368720Online:28...

We propose the use of mutation-based error injection to guide generation high-quality diagnostic test patterns. A software-based fault localization technique is employed derive a ranked candidate list suspect statements. Experimental results for set Verilog designs demonstrate that finer resolution can be achieved by patterns generated proposed method.

Dual-V th design is an effective leakage power reduction technique at behavioral synthesis level. It allows designers to replace modules on non-critical path with the high-V implementation. However, existing constructive algorithms fail find optimal solution due complexity of problem and do not consider on-chip temperature variation. In this paper, we propose a two-stage thermal-dependent minimization algorithm by using dual-V library during synthesis. first stage, quantitatively evaluate...

High temperature adversely impacts on reliability, performance, and leakage power of ICs. In behavioral synthesis, both resource usage allocation binding influence the final thermal profile. Previous thermal-aware syntheses only focused binding, ignoring allocation. This paper proposes synthesis with According to density feedbacks from simulation, we allocate number resources under area constraint. Our flow effectively controls peak creates even densities among "different" "same" types....