A5101467786- Interconnection Networks and Systems
- Parallel Computing and Optimization Techniques
- Advanced Data Storage Technologies
- Advanced Memory and Neural Computing
- Supercapacitor Materials and Fabrication
- Optical Coherence Tomography Applications
- Dark Matter and Cosmic Phenomena
- Low-power high-performance VLSI design
- Laser Material Processing Techniques
- Earthquake and Disaster Impact Studies
- Random lasers and scattering media
- Video Coding and Compression Technologies
- Radiation Detection and Scintillator Technologies
- Neutrino Physics Research
- Earthquake and Tsunami Effects
- Magnetic properties of thin films
- Embedded Systems Design Techniques
- Nuclear Physics and Applications
- 3D IC and TSV technologies
- Geotechnical Engineering and Soil Stabilization
- Non-Invasive Vital Sign Monitoring
- Phase-change materials and chalcogenides
- Particle physics theoretical and experimental studies
- Digital Holography and Microscopy
- Atomic and Subatomic Physics Research
The University of Texas at Arlington
2024
Korea University Medical Center
2024
Virginia Tech
2022
Parc Científic de la Universitat de València
2022
Universitat de València
2022
Dankook University
2013-2021
Samsung (South Korea)
2003-2018
Gyeongsang National University
2016
Pusan National University
2013
Chungbuk National University
2010-2012
Abstract The ICARUS liquid argon time projection chamber (LArTPC) neutrino detector has been taking physics data since 2022 as part of the Short-Baseline Neutrino (SBN) Program. This paper details equalization response to charge in (TPC), well data-driven tuning simulation ionization signals and electronics noise. procedure removes non-uniformities TPC space time. work leverages copious number cosmic ray muons available at surface. signal shape applies a novel that tunes match what is...
We report on an approach to exploit multiple light scattering by shaping the incident wavefront in optical coherence tomography (OCT). Most of reflected signal from biological tissue consists multiply scattered light, which is regarded as noise OCT. A digital mirror device (DMD) utilized shape such that maximal energy focused at a specific depth highly sample using coherence-gated reflectance feedback. The proof-of-concept experiment demonstrates this enhances depth-selective focusing...
Task scheduling and core mapping have a significant impact on the overall performance of network chip (NOC). In this paper, unified task algorithm called UNISM is proposed for different NOC architectures including regular mesh, irregular mesh custom networks. First, model combining introduced using mixed integer linear programming (MILP). Then, novel graph to consider irregularity estimate communication energy latency, since number hops not accurate enough To make MILP-based scalable,...
We report the enhancement in obtained signal and penetration depth of 2-D depth-resolved images that were taken by shaping incident wavefront optical coherence tomography (OCT). Limitations to noise ratio (SNR) OCT are mainly due multiple scattering, which have been effectively suppressed controlling using a digital mirror device (DMD) combination with spectral-domain OCT. The successful enhancements SNR demonstrated wide-range tissue phantoms, reaching up 92%. hidden structures inside...
In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) not only with homogeneous cores on regular mesh architecture as done by most previous mapping algorithms but also heterogeneous irregular or custom architecture. As main contribution, develop simple yet efficient interconnection matrix that models any task graph network. Then, problem is exactly formulated an MIQP...
In this paper, we present a partitioning, mapping, and routing optimization framework for energy-efficient VFI (voltage-frequency island) based network-on-chip. Unlike the recent work [10] which only performs partitioning together with voltage-frequency assignment given mesh network layout, our consists of three key VFI-aware components, i.e., routing. Thus technique effectively reduces overheads such as mixed clock FIFOs voltage level converters by over 82% energy consumption 9% compared...
In this paper, we present a partitioning, mapping, routing and interface optimization framework for energy-efficient voltage-frequency island (VFI) based networks-on-chip. Unlike the recent work that performs tile partitioning only with assignment given mesh network layout, our consists of three key VFI-aware components, i.e., core voltage frequency assignment, path allocation. addition, develop VFI its insertion algorithm to easily satisfy performance constraints. Our methodology makes...
In this article, we propose novel and global Architecture-Aware Analytic MAPping (A3MAP) algorithms applied to Networks-on-Chip (NoCs) not only with homogeneous Processing Elements (PEs) on a regular mesh network as done by most previous application mapping but also heterogeneous PEs an irregular or custom network. As the main contributions, develop simple yet efficient interconnection matrix that can easily model any core graph Then, problem is exactly formulated Mixed Integer Quadratic...
Multiple light scattering in tissue limits the penetration of optical coherence tomography (OCT) imaging. Here, we present in-vivo OCT imaging a live mouse using wavefront shaping to enhance depth. A digital micro-mirror device (DMD) was used spectral-domain system for complex an incident beam which resulted optimal delivery energy into deep tissue. Ex-vivo chicken breasts and ear tissues showed enhancements strength image signals depth, tail provided multilayered structure inside tissue,...
In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) not only with homogeneous cores on regular mesh architecture as done by most previous mapping algorithms but also heterogeneous irregular or custom architecture. As main contribution, develop simple yet efficient interconnection matrix that models any task graph network. Then, problem is exactly formulated an MIQP...
Networks-on-chip (NoCs) may interface with lots of synchronous dynamic random access memories (SDRAM) to provide enough memory bandwidth and guaranteed quality-of-service for future systems-on-chip (SoCs). SDRAM is commonly controlled by a subsystem that schedules requests improve efficiency latency. However, still performance bottleneck in the entire NoC. Therefore, memory-aware NoC optimization has attracted considerable attention. This paper presents router an explicit SDRAM-aware flow...
In systems-on-chip (SoCs), a microprocessor demands guaranteed synchronous dynamic random access memory (SDRAM) latency whereas most of the other cores are served as best-effort packet. However, priority service for causes SDRAM utilization and an overall system to be degraded critically. addition, data size requested by various is not matched with granularity such that further deteriorated. this paper, we propose application-aware networks-on-chip (NoCs) design efficient access, which can...
In this paper, we present a partitioning, mapping, and routing optimization framework for energy-efficient VFI (voltage-frequency island) based network-on-chip. Unlike the recent work [10] which only performs partitioning together with voltage-frequency assignment given mesh network layout, our consists of three key VFI-aware components, i.e., routing. Thus technique effectively reduces overheads such as mixed clock FIFOs voltage level converters by over 82% energy consumption 9% compared...
In this paper, we present an NoC (Networks-on-Chip) router with SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce latency. Moreover, our multi-scheduling scheme performed by the multiple routers helps achieve better SDRAM performance save hardware cost of platform. Experimental results show that improves latency 18% 4.9% average over 42% saving gate count platform dual subsystem.
We have demonstrated the creation of polarization-dependent nanogratings with a period about 250 nm on surface sapphire by scanning femtosecond laser beam appropriate irradiation conditions. Laser fluence range for nanograting self-formation was very narrow in slow scan mode. The grating depth variation observed atomic force microscope image analysis. To see composition distribution nanostructure, we carried out Auger signal In addition, found new periodic structure few μm and discussed...
In this paper, we propose the first chemical-mechanical polishing (CMP) aware application-specific three-dimensional (3D) network-on-chip (NoC) design that minimizes through-silicon-via (TSV) height variation, thus reduces its bonding failure, and meanwhile optimizes conventional NoC objectives. Our 3D assigns cores to proper silicon layers, determines topology, allocates routing paths, then floorplans cores, routers TSV arrays by a CMP-aware manner. The key idea behind flow is determine...
A wide tuning range wavelength swept laser for high axial resolution optical coherence tomography reported. Here, a parallel configuration of quantum dot semiconductor amplifier (SOA) and well SOA is utilised broadband source. The total scanning over 210 nm (192 at 10 dB) from 1153 to 1366 To investigate the feasiblity light source, demonstrated an frequency domain imaging (OFDI) system. system sensitivity 101 dB reported 6.0 µm in air achieved. Finally, ex vivo OFDI human breast tissue performed.
The conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve performance, the adaptive bank-interleaved for a DRAM technology proposed. In our approach, addresses are efficiently rearranged using bank-flipping technique given application configuration. configure based on bank interleaving metric in systematic way invoked. Considering image processing applications, algorithm, analysis, design, evaluation of proposed...
일반적으로 롤/요 평면상의 nutation 운동이 있는 피치 모멘텀 바이어스 시스템을 정지궤도 위성인 통신위성에서 주로 사용되어 왔으나 본 논문에서는 저궤도 위성의 경우에 대해 최소 휠 개수인 2개 반작용휠로 구성된 제어방식으로 피치축과 롤축 자세제어를 수행하는 방안을 살펴보았다. PI-제어기를 사용한 제어 방식의 경우 베어링 마찰 등 반작용휠에 가해지는 외란에 대한 강건성 보장을 해석적으로 분석하였으며, 자세에러 측정치와 요축 선형 제어기 설계를 위한 전달함수를 제시하였고, 시스템에 이해도를 높이고, 외란 영향 및 크기 필요한 설계 인자 선정을 위해 분석을 수행하였다.아울러 PID-제어기를 시스템의 롤/요축 자세제어 설계결과 시뮬코타키나발루레이션 결과를 제시하였다. In general, the pitch momentum biased system that induces inherently nutational motion in roll/yaw plane, has been...
Many-core chips interconnected by networks-on-chip (NoC) are increasingly challenged the tight power consumption constraints. The concept of voltage and frequency island (VFI) which has been recently introduced for achieving fine-grain core-level management fits well with an NoC design style. This paper will discuss some recent advancement VFI optimizations many-core/NoC designs. We also other research challenges low-power designs from electronic system level (ESL) perspective.
In this paper, we propose the first chemical-mechanical polishing (CMP) aware application-specific three-dimensional (3D) network-on-chip (NoC) design that minimizes through-silicon-via (TSV) height variation, thus reduces its bonding failure, and meanwhile optimizes conventional NoC objectives. Our 3D assigns cores to proper silicon layers, determines topology, allocates routing paths, then floorplans cores, routers TSV arrays by a CMP-aware manner. The key idea behind flow is determine...
In this paper, we propose an application-aware networks-on-chip (NoC) design for efficient SDRAM access. order to provide short latency priority memory requests with few penalties, a packet is split into several packets which then are scheduled by the proposed flow controller in router. Moreover, our NoC further improves performance matching application access granularity granularity. Experimental results show that on average 32.7% latency-sensitive cores and 3.4% utilization compared [1].