ABSTRACT An LC quadrature voltage‐controlled oscillator ( ‐QVCO) with novel compensated coupling networks to achieve both low supply sensitivity and phase enhancement is proposed. Designed fabricated in a standard 0.18‐μm CMOS process, the proposed QVCO improves noise rejection by more than 16.72 dB compared conventional ‐QVCO achieves error of < 0.86° within frequency tuning range from 3.32 3.52 GHz, whereas occupying core area 504 × 400 μm 2 consuming 3.2 mA including bias circuitry,...

A voltage-controlled oscillator (VCO) with VCO-gain (KVCO) variation compensation is proposed to reduce KVCO in a current-mode logic (CML) ring by introducing cross-coupled pair capacitive degeneration that mitigates the nonlinearity of KVCO. Designed and fabricated standard 0.18-μm CMOS process, VCO can be tuned from 1.78 2.53 GHz, gain less than 14.01%, while occupying core area 0.185 × 0.081 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

The causes of supply noise-induced frequency variation in CML ring oscillators are investigated and a novel circuit topology that reduces the sensitivity is presented. It shown this technique only slight reduction maximum oscillation maintains nearly same random jitter generation while greatly reducing sinusoidal caused by power variation. Measurement results from prototype chip fabricated 0.18 μm CMOS process verify effectiveness proposed technique.

This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise ultra-low power performance. By employing the mixed switching scheme, segmented capacitive digital-to-analog (CDAC) arrays as well synchronous data-weighted averaging (DWA) calibration block, SAR ADC can operate from 1.8 V down to 0.8 at...

This letter presents an L-band highly linear differential low noise amplifier (LNA) in a standard 90-nm CMOS process. A wide range derivative superposition technique is proposed to maximize the third-order intercept point (IP3), and at same time, minimize intermodulation distortion (IMD3) over input power range. The LNA chip achieves measured OIP3 of +33.7 dBm IMD3 -65 dBc with -15 power. peak gain minimum figure are 15.4 dB 1.36 1.27 GHz, respectively. consumes 40 mA from 3.3-V supply.

Multiple loops have been used extensively to enhance the system performance in various applications. However, increasing complexity of multi-loop systems also makes them much more difficult analyze and implement. In this paper, a new methodology is proposed. proposed framework, are regarded be built upon sub-modules cascade, parallel adding, feedback units, then, they simplified following certain procedure based on correlation Bode characteristics segmented sub-modules. Applying methodology,...

The effects of supply-induced frequency variations on single-ended tuning LC voltage-controlled oscillator (VCO) which degrade the jitter performance clock are investigated. first-order impact supply sensitivity is that varactor's effective capacitance varies with voltage, other second-order impacts attributed to commonly used capacitive bank and cross-coupled pairs. A compensation technique based complementary varactors improve VCO proposed no extra power dissipation, nor phase noise...

Thermo-structural weak coupling model was adopted in numerical simulation of laser-arc hybrid T-joint welding. Gauss surface heat source and Rotary-Gauss body were used to form a combined the temperature field analysis simulate arc laser source. The overlaying welding test 304 stainless steel carried out, weld molten pool morphology obtained by metallographic corrosion test. results show that combination can better process. effects power, power speed on residual stress deformation studied...

Abstract A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver (TRx) designed in a 28-nm complementary metal-oxide-semiconductor (CMOS) process is presented this article. voltage-mode (VM) driver featuring 4-tap reconfigurable feed-forward equalizer (FFE) employed the quarter-rate transmitter (TX). The half-rate receiver (RX) incorporates continuous-time linear (CTLE), 3-stage high-speed slicer with multi-clock-phase sampling, and clock data recovery (CDR). experimental results show that TRx operates...

The locking range of injection-locked frequency dividers is investigated and it shown that the presence nonlinearities, such as those exhibited in a current mode logic (CML) D flip-flop (DFF)-based divider, can result wider range. A new approach to evaluate nonlinearities described. divider topology benefiting from nonlinearity presented exhibits both higher operating frequencies similar compared conventional CML DFF-based topology. chip was fabricated through TSMC 90-nm CMOS process.

Circulator is a key component in full-duplex wireless and radar detection systems. In this letter, dual interference-canceling active quasi-circulator proposed to enhance the isolation capability over range of 1-7 GHz. The circulator fabricated standard 0.18-μm CMOS process occupying 1.03 mm × 0.55 including pads. Measurement results demonstrate more than 36-dB from Tx Rx within 6-GHz bandwidth. designed good candidate for duplexers allow integrated transmitter receiver share single antenna...

This letter presents a 100-Gb/s CMOS PAM-4 transimpedance amplifier (TIA) with multi-milliampere maximum linear input current. A low-noise high-linearity TIA architecture is proposed, leveraging the reconfigurable front-end (FE) and continuous time equalizer (CTLE) synced at multiple gain modes. Implemented in 28-nm technology, achieves bandwidth of more than 24 GHz 65 dBΩ, while showing an inputreferred noise current density 10.4 pA/√Hz. The reaches 2.2 mApp total harmonic distortion (THD)...

The recent boom of XGS-PON (10Gb/s symmetrical passive optical network) mandates low cost the massive volume consumer market. Critically, time-division multiplexing method in upstream PON demands burst-mode (BM) receiver (Rx) with minimum settling time so that each user can capture more effective bandwidth. BM-Rx needs to execute 3R functions re-amplify (TIA), reshape (LA) and re-time (CDR) successively. Since amplitude incoming burst signal vary by than 1000x from microampere milliampere,...

A 12-bit successive approximation register analog to digital converter (SAR ADC) built in an intelligent platform management interface (IPMI) system on chip (SoC) is proposed this paper. The work designed and fabricated SMIC 0.13 μm CMOS process, using the fully differential C-R hybrid (DAC) structure. Scaling capacitor adopted improve precision reduce area. Through optimization of placement routing, DAC achieves high precision. Besides, a multi-stage comparator designed, offset calibration...

This letter presents a 5–6-GHz CMOS beamforming transceiver front-end with high linearity and low power consumption for fiber-to-the-room (FTTR) all-optical Wi-Fi solution, which can greatly reduce the transmission eliminate signal mutual interference among access points compared traditional architecture, by aggregating beams of multichannel. The transmitter (TX) employs high-linearity amplifier, variable-gain 5-bit passive attenuator (ATT), 4-bit phase shifter (PS). receiver (RX) is...

This brief presents a 54–68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in 40 nm CMOS process. The first stage adopts current reuse cascaded common-source (CS) structure shunt RC feedback to maximize the gain minimize DC consumption boost efficiency, while second is cascode two built-in linearizers enhance much further. Based on proposed structure, fabricated PA exhibits measured output of 1-dB compression point, saturated power, added (PAE) AM-PM distortion...

A 1.5-2.5 GHz current-mode logic (CML) ring oscillator-based supply-insensitive phase-locked loop (PLL) employing two different topologies of CML oscillators that compensate for the supply variations is presented. In addition, an on-chip calibration scheme designed to ensure voltage-controlled (VCOs) operate at optimum operating point where PLL achieves nearly best power rejection. This work shows more than 96% reduction in sensitivity VCOs compared with conventional topology. sinusoidal...

A novel circuit topology for CMOS CML ring oscillators that reduces the supply sensitivity is presented. It shown this technique causes only a slight reduction in maximum frequency of oscillator and maintains same random jitter generation while greatly reducing sinusoidal caused by power variation. Measurement results from prototype chip fabricated 0.18µm process verify effectiveness proposed technique.

A dual-path open-loop slew-rate controlled CMOS driver is presented. The proposed output incorporates a delay-locked loop (DLL) to minimize the variation over process, voltage and temperature (PVT). structure introduced cancel high-frequency components of signal. Simulation using Global Foundry 0.18μm process shows that achieves less than 0.66V/ns operating at 500 Mbps 16 corners, corresponding 56% reduction compared with conventional driver.

The surge of internet bandwidth recently has accelerated the upgrade Passive Optical Network (PON) from 1.25Gb/s GPON to 10Gb/s class XGS-PON with massive volume. As a key component, burst-mode transimpedance amplifier (BM-TIA) is required cope BM data multiple users. Previously, high performance BM-TIAs were made mostly by SiGe [1]–[3], contrasting prospect economics. At least three issues have hindered CMOS being widely employed in BM-TIA compared SiGe. 1) Noise: relatively poor analog as...

A four-stage continuous-time linear equalizer (CTLE) in a 28-nm CMOS process is presented. The proposed CTLE provides peaking gain at Nyquist frequency of ~16 GHz, as well mid-frequency boosting for low-frequency channel-loss compensation. An ultrafine gain-tuning scheme employing an extra positive-feedback path and analyzed, which enables both large range fine steps. dc covers wide from −3.81 to 11.29 dB with step size less than 0.3 dB, the can be adjusted −3.52 13.48 0.9 while providing...

In this paper, we present a linear optical receiver for 112-Gb/s PAM-4 link. We propose transimpedance front-end that optimizes thermal noise, power supply noise rejection, linearity and bandwidth altogether. The pseudo-differential structure is employed to achieve both low good rejection. A amplifier (TIA) gain control technique proposed improve at topology transistor level while maintaining stability. An NIC-CTLE combo extends with optimized frequency response. Designed in 130nm SiGe...