A5101651027- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Optical Network Technologies
- Advancements in PLL and VCO Technologies
- Advanced Optical Sensing Technologies
- Radio Frequency Integrated Circuit Design
- Inertial Sensor and Navigation
- Target Tracking and Data Fusion in Sensor Networks
- Advanced Photonic Communication Systems
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Measurement and Detection Methods
- VLSI and Analog Circuit Testing
- Wireless Networks and Protocols
- Advanced Fluorescence Microscopy Techniques
- Thin-Film Transistor Technologies
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Wireless Body Area Networks
- Bluetooth and Wireless Communication Technologies
- Semiconductor materials and devices
- Simulation and Modeling Applications
- Advanced Optical Network Technologies
- Neural Networks and Reservoir Computing
- Analog and Mixed-Signal Circuit Design
- 3D IC and TSV technologies
Southern University of Science and Technology
2019-2025
Peng Cheng Laboratory
2022-2024
University of Hong Kong
2013-2016
Hong Kong University of Science and Technology
2013-2016
Shandong Institute of Automation
2012
Chongqing University of Posts and Telecommunications
2010
An 18-Gb/s fully integrated optoelectronic circuit for short-distance communications is realized in the TSMC 65-nm CMOS process. The system consists of a on-chip photodetector, an inverter-based cascode transimpedance amplifier, DC offset cancellation buffer, main three-stage tunable continuous-time linear equalizer, two-stage modified limiting network, adaptive equalization loop, low dropout regulator, and 50-Ω termination output buffer. P-Well/Deep N-Well photodetector improves bandwidth...
This paper presents a digitally controlled 1-V 30-Gb/s 1.37-pJ/b optical receiver in 65-nm CMOS technology. consists of an inverter-based inductive transimpedance amplifier, fully integrated low-dropout regulator, main three-stage-cascaded continuous-time linear equalizer (CTLE), two-stage limiting and output driver. The CTLE three cascaded stages with different peaking frequencies (5, 12, 20 GHz) offering 16 dB adjustable low-frequency gain to accommodate photodetector (PD) characteristics....
This paper presents a 65-nm CMOS, 1-V, 1.37-pJ/bit optical receiver with embedded equalizer, enabling adaptability to overcome channel losses and component variations. The digitally-controlled continuous-time linear equalizer (CTLE) consists of three cascaded tunable peaking stages offering 16-dB adjustable low-frequency gain. Optical measurement results 30-Gb/s photodetector (PD) show that the achieves 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This letter presents the design, measurement results, and modeling formula of a P-well/deep N-well photodetector (PD) realized in standard 65-nm complementary metal-oxide-semiconductor without process modification. With 0.5-V reverse bias (VPD), measured dc responsivity to an 850-nm light source is 51 mA/W -3-dB bandwidth 500 MHz. Besides, seamless cosimulation PD following receiver circuits are presented. Optical results show that under VPD, optical achieves new record data rate 9 Gb/s for...
A 65-nm CMOS monolithic optical receiver IC with on-chip photodetector (PD) using the p-well/deep-n-well (PW/DNW) junction is presented for short-range communication 850-nm wavelength. An adaptive continuous-time linear equalizer (CTLE) 33-dB tunable gain employed to compensate limited PD responsivity and bandwidth. For PRBS-15 inputs, achieves record data rates efficiencies of 9 Gb/s at 5.35 pJ/bit 18 2.7 biased in 0.5-V standard mode 12.3-V avalanche mode, respectively. The core chip...
Abstract This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and reference-less clock data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ gain, 20.4-GHz −3-dB bandwidth, 12-dB DC gain tuning range. measurements the VGA’s...
A 30-Gb/s differential limiting amplifier (LA) composed of three cascaded stages is presented. Fabricated in 65-nm CMOS process, the proposed LA yields a typical gain 31.1 dB and -3-dB bandwidth 22.1 GHz while consuming 23 mW from 1-V supply. The measured tuning range 10 with maximum step size less than 1 dB. DC offset cancellation implemented by feedback loop consisting low-pass filter (LPF) an amplifier. Optical measurements demonstrate that degradation RMS jitter for 25-Gb/s PRBS due to...
Wireless Industrial communication technology becomes increasingly important and has attracted widespread attention for industrial applications. WIA-PA (Wireless Networks Automation-Process Automation) standard is one of the three international wireless standards. Because operating on shared ISM band, anti-interference a key issue adopts adaptive channel hopping mechanism to coexist with other interfering systems. However, current does not present any specified scheme mechanism. In this...
In this paper, we present a linear optical receiver for 112-Gb/s PAM-4 link. We propose transimpedance front-end that optimizes thermal noise, power supply noise rejection, linearity and bandwidth altogether. The pseudo-differential structure is employed to achieve both low good rejection. A amplifier (TIA) gain control technique proposed improve at topology transistor level while maintaining stability. An NIC-CTLE combo extends with optimized frequency response. Designed in 130nm SiGe...
A 65-nm CMOS limiting amplifier based on three stages of a modified Cherry-Hooper with offset cancellation is presented. The trade-off between the range and input-referred noise discussed. variations gain bandwidth due to PVT corners are achieves 32.1 dB 21.6 GHz bandwidth, 1-V supply power dissipation 33.3 mW.
A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as P-terminal, a wider depletion region achieved deeper position from surface. This photodetector achieves −3-dB bandwidth of 1.1 GHz and responsivity 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using proposed APD able to operate 4 Gbps.
This paper presents, for the first time, an optical-to-mm-wave modulator SoC with integrated 850-nm wavelength optical receiver front-end short-range backhaul connectivity in emerging fiber-wireless mobile networks. Realized 65-nm CMOS, achieves -3dBm input sensitivity at 4Gb/s 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> BER. The directly up-converts de-multiplexed 2Gb/s I/Q NRZ data to a QPSK signal 60GHz. consumes 78mW and...
With the increasing processing data traffic of big data, 5G networks, 8K video and other applications, existing 100 Gb/s transmission system is no longer sufficient. This paper proposes a 400 Ethernet (400 GbE) verification platform based on FPGA (Field-Programmable Gate Array), including TRX (transceiver) PMA (Physical Medium Attachment), QSFP-DD (Quad Small Form-factor Pluggable Double Density) optical modules fibers, 8-lane MCB (Module Compliance Board), which used for loopback outgoing...
This paper presents the measured performance of different photodetector (PD) structures in a standard 65-nm CMOS technology. All photodiodes and phototransistors are tested using an 850-nm laser source through 62.5-μm-diameter multi-mode fiber. Measurement simulation results show that integrated with proper equalization can support > 10 Gbps systems.
This study conducts research on the performance of NRZ 100Gb/s modulation, as well its scalability to PAM4 400Gb/s and 800Gb/s data-rate. The FPGA verification platform consists a CMOS SerDes, an InfiniBand Extended Data Rate (IB EDR) module, 4-lane QSFP28 compliance board, loop-back on-board optics (OBO) 100G Evaluation Board, with electrical/optical I/O assembly or silicon-photonic (Si-Ph) chip module. follows Common Electrical (CEI) standard. For high-speed data-rate 100 Gbps through...
This paper presents a peak-tunable PAM-4 linear equalizer for 200-Gb/s communication in 130-nm SiGe BiCMOS process. It consists of two stage continuous-time equalizers (CTLE) and an output driver. The feedforward degeneration techniques are employed to realize multiple peaks at high, middle low frequency points, respectively. Moreover, the can reach maximum 20.6-dB compensation with fixed peaking 51 GHz. simulation results show that 18-dB lossy channel, proposed provides 53-GHz bandwidth...
A complete 25Gb/s PAM4 optical transceiver chipset using commercial 10G-lasers for 10km single-mode fiber is presented. Measurement results demonstrate <−12dBm sensitivity across all temperatures and <30pJ/bit power efficiency.
A transit-time-enhanced silicon photodetector is proposed and fabricated in standard CMOS without process modification. By adopting the lateral interleaved junction, this PD features a 0.13-A/W responsivity doubled 10.43-GHz transient-time bandwidth. Moreover, clear 10-Gb/s 850-nm optical eye diagram observed.
This paper describes an inverter-based receiver analog front-end design using T-coil technique implemented in a 40nm CMOS process. The proposed can separate the capacitance of PAD and preamplifier itself, to achieve total bandwidth enhancement ratio 2.7. continuous time linear equalizer(CTLE) adopts negative feedback loop generate low frequency zero-pole pair slower down compensation slope. simulation result shows that transimpedance gain system is 76.5 dBΩ under 37GHz. input referred noise...