A5019079124- Photonic and Optical Devices
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Semiconductor Lasers and Optical Devices
- Semiconductor materials and devices
- Optical Network Technologies
- VLSI and Analog Circuit Testing
- Analog and Mixed-Signal Circuit Design
Southern University of Science and Technology
2021-2024
This paper discusses a 56-Gb/s PAM4 receiver analog-front end (AFE) implemented in TSMC 40-nm CMOS process. The system consists of differential 100- Ω termination, two-stage continuous-time linear equalizer (CTLE), variable gain amplifier (VGA), and an output buffer. source-degenerated transconductance stage inverter-based transimpedance (TIA) with source follower structure are adopted for both CTLE VGA. utilization can solve the harsh DC operation problem conventional TIA extend bandwidth....
With the exponential growth of artificial intelligence systems and cloud computing, next-generation wireline transceivers are aiming for data rates 800GbE/1.6TbE, requiring 224Gb/s per lane. Potential long-reach (LR) solutions [1] include: 1) ADC/DSP-based schemes; 2) PAM-6/PAM-8/OFDM modulation or 3) PAM-4 retimers with embedded CDRs equalizers. While all above schemes based on differential signaling, there has been recent interest in single-ended schemes, such as 2D/3D interposer, UCIe,...
The growing demand for cloud computing and artificial intelligence applications pushes wireline transceivers to higher data rates. DSP-based transmitters (TX) receivers (RX) have achieved 224Gb/s [1–2], but unfortunately consume substantial power. Furthermore, SerDes places more stringent demands on the signal integrity of passive components, such as connectors, channels, packages. In contrast, single-ended scheme may be a practical cost-effective solution First, it doubles throughput...
This paper presents a dual-coupled single-ended (SE) receiver with crosstalk cancellation and signal reutilization (XTCR) technique in 28 nm CMOS process. The asymmetric-inductor SE to differential converter (S2D) is proposed eliminate the mismatch at its pseudo-differential outputs. conventional active extraction (AXTE) techniques are adopted one of two lanes, respectively. Compared one, AXTE can compensate for higher insertion loss without extra power consumption, improve measured...
A 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 56 Gb/s 0.78-pJ/b four pulse-amplitude modulation (PAM-4) single-ended multiple-input multiple-output (MIMO) crosstalk cancellation and signal reutilization (XTCR) receiver (RX) is investigated for medium-reach (MR) backplane communications. An XTCR scheme based on active extraction (A-XTCR) proposed to improve the...
This paper presents a peak-tunable PAM-4 linear equalizer for 200-Gb/s communication in 130-nm SiGe BiCMOS process. It consists of two stage continuous-time equalizers (CTLE) and an output driver. The feedforward degeneration techniques are employed to realize multiple peaks at high, middle low frequency points, respectively. Moreover, the can reach maximum 20.6-dB compensation with fixed peaking 51 GHz. simulation results show that 18-dB lossy channel, proposed provides 53-GHz bandwidth...
This paper presents a 112-Gb/s single-ended (SE) PAM-4 transceiver front-end for the reach-extension module in 130 nm SiGe BiCMOS technology. The transmitter is based on differential-to-SE driver where negative capacitance scheme introduced to extend its bandwidth. receiver features low-mismatch SE-to-differential (S2D) amplifier and an inductor-reuse continuous-time linear equalizer (CTLE). In S2D, both asymmetric reused inductor compensation techniques are implemented eliminate mismatch at...