A5004818677- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- CCD and CMOS Imaging Sensors
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Optical Network Technologies
- Neuroscience and Neural Engineering
- Semiconductor materials and devices
Southern University of Science and Technology
2018-2024
This brief presents a picowatt CMOS voltage reference with ultra-low supply and wide temperature range. Biased by PMOS leakage current, power consumption are achieved. The range is enlarged using the increased bulk diode current modulation (BDLCM) effect at high temperature. proposed design implemented in standard 0.18- μm process. measurement results show that, circuit can provide an average of 118.1 mV deviation 1.3 mV. minimum 250 line sensitivity (LS) 0.3 %/V. coefficient (TC) 73.5...
With the exponential growth of artificial intelligence systems and cloud computing, next-generation wireline transceivers are aiming for data rates 800GbE/1.6TbE, requiring 224Gb/s per lane. Potential long-reach (LR) solutions [1] include: 1) ADC/DSP-based schemes; 2) PAM-6/PAM-8/OFDM modulation or 3) PAM-4 retimers with embedded CDRs equalizers. While all above schemes based on differential signaling, there has been recent interest in single-ended schemes, such as 2D/3D interposer, UCIe,...
A Power-area-efficient output-capacitorless low- dropout (OCL-LDO) regulator with fast transient response is presented in this paper. The proposed technique permits the to achieve small undershoot (overshoot) when load steps up (down) and consumes little extra power. LDO has been implemented fabricated a 0.18- μm CMOS process. It occupies an active area of0.0071mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . simulated results have...
The Internet of Things (loT) is developing rapidly, and energy harvesting (EH) provides the power source impetus for it. Still collected from EH generally underfed, which obliges powered modules to achieve low consumption as much possible. Hence, growth voltage quiescent current designs are pushed forward. For applications with sub-10µA under low-supply (200-300mV), such sensors monitoring, SRAM [1], designing an additional regulator overburdened one solution reference (VR) integrated output...
In this paper, a fully-on-chip, NMOS low dropout voltage (LDO) regulator with capacitance multiplier used for improving the stability and transient response is proposed. This compensation technology emulates large value at gate of pass FET high fast response. The chip area much reduced compared to conventional design. proposed LDO designed in 0.18-μm CMOS process consumes 13.2 μA quiescent current 0.1 V 1.0 output voltages. It does not require any external capacitor.
This paper presents a low power subthreshold CMOS voltage reference (CVR) with current loading capability. Based on the classical 2T CVR to achieve temperature coefficient (TC), sourcing PMOS is appropriately biased through local negative feedback loop. Current capability achieved without relying an output buffer. The proposed designed in standard 0.18-μm process. Simulation results show that capable of delivering 300 μA while generated Vref has less than 0.42% reduction. minimum supply 0.5...