This paper presents a low-power and high-precision voltage current reference (VCR) in one simple circuit. The is derived from the threshold difference between an I/O (i.e., 3.3-V NMOS) standard 1.8-V transistors with temperature-independent bias current, divided by temperature-insensitive resistor. resistor made up series connection of proportional-to-absolute-temperature (PTAT) NWELL complementary-to-absolute-temperature (CTAT) high-resistance poly series. Implemented 0.18-μm CMOS process,...

This brief presents a novel ultralow power CMOS voltage reference (CVR) with only 4.6-nW consumption. In the proposed CVR circuit, proportional-to-absolute-temperature is generated by feeding leakage current of zero-Vgs nMOS transistor to two diode-connected transistors in series, both which are subthreshold region; while complementary-to-absolute-temperature created using body diodes another transistor. Consequently, low-power operation can be achieved without requiring resistors or bipolar...

This brief presents a CMOS voltage reference for Internet-of-Things applications, which requires ultra-low power and high insensitivity to variation from ambient energy harvesting. proposed novel self-regulating circuit significantly diminish the line sensitivity (LS) of supply without using any amplifiers or passive components. All transistors in this design work subthreshold region low operation. The is fabricated standard 0.18-μm process. measurement results show that, could provide an...

This brief presents a CMOS voltage reference for ultra-low-power applications, such as in implementable medical devices and energy harvesting-based wireless sensor nodes. In these excellent capabilities to reject interference from power sources work low extend survival periods are critical the references. A transistor size-ratio determined current generator with high process independence is implemented by two same-threshold-voltage NMOS transistors, hence obtaining precise an active load....

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors a single BJT is presented in this brief. The proposed sub-BGR consists of novel complementary-to-absolute-temperature (CTAT) generator based on scaled emitter-base BJT, an improved proportional-to-absolute-temperature (PTAT) stacking <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML"...

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly modifying conventional scheme, the PSRR of BGR significantly enhanced. PSRRs two different techniques have been formulated verified. Moreover, design considerations are presented, taking into account critical parasitic capacitor's effect in PSRR. To our knowledge, first time literature...

In this brief, a low-voltage low-temperature- coefficient (TC) subthreshold CMOS voltage reference (CVR) is presented. The proposed CVR employs the ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> of different-threshold and same-threshold nMOS transistor pairs to generate complementary-to-absolute-temperature proportional-to-absolute-temperature voltages, respectively. Low TC with small variations high power supply ripple rejection...

InAlAs/InGaAs high electron mobility transistors (HEMTs) on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation fmax are reported. An HEMT 100-nm gate length width of 2 × 50 μm shows excellent DC characteristics, including full channel current 724 mA/mm, extrinsic transconductance gm.max 1051 mS/mm, drain—gate breakdown voltage BVDG 5.92 V. In addition, this device exhibits = 249 GHz 415 GHz. These results were obtained by fabricating asymmetrically recessed...

This brief presents a fully integrated low-power, low noise bandgap reference (BGR) with load driving capability. With the BGR core resistors functioning as feedback network of current sourcing power transistor, proposed saves chip area, reduces while supporting driving. The circuit is implemented in two different processes for performance comparison, namely <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math...

A dual-output CMOS voltage reference is presented for ultra-low power applications that require two or more different references. The VREF1 designed by employing the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> difference between devices to compensate temperature coefficient (TC) of thermal voltage. xmlns:xlink="http://www.w3.org/1999/xlink">REF2</sub> generated feeding a current mirrored from first voltage's supply into...

This brief presents a nano-ampere CMOS current reference (CCR) for low power application with wide temperature range from -40°C to 120°C. The is generated by the division of temperature-independent voltage and resistance in simple way. based on threshold difference between two same-type NMOS transistors different channel lengths working subthreshold region, while made up poly resistors, whose coefficients are opposite. By designing allow small resistance, CCR circuit takes chip area...

A low-power CMOS voltage reference with active-feedback frequency compensation is proposed for power-constrained IoT applications whereby power supply ripple rejection (PSRR) performance critical the survival of devices. The consists MOS transistors operating in sub-threshold region to allow low-voltage and operations. An technique has been used make loop stable improve PSRR a very small capacitor while allowing relatively large output capacitor. circuit fabricated standard 0.18-μm process....

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly modifying conventional scheme, the PSRR of BGR significantly enhanced. PSRRs two different techniques have been formulated. To our knowledge, first time in literature explicitly demonstrating how due to compensation. The feedback loop stability also analyzed. simulated an example using...

Summary An amplifier‐offset‐insensitive complementary metal‐oxide‐semiconductor (MOS) voltage reference (CVR) circuit with high power supply ripple rejection (PSRR) is presented. Due to the novel structure of employing subthreshold MOS transistors, proposed CVR can suppress direct current offset effects internal amplifier. Design considerations in optimizing and area consumptions improving PSRR are The implemented a standard 0.18 μm process. Measured results show that run down‐to 0.9 V...

A CMOS sub-bandgap voltage reference (sub-BGR) with single BJT and two resistors is presented in this paper. The proposed sub-BGR structure generates the complementary-to-absolute-temperature (CTAT) not only occupying small chip area consuming nA-level current, but also achieving low sensitivity to current mirror mismatches. CTAT a scaled emitter-base of proportional-to-absolute-temperature (PTAT) based on stacking ΔVGS sub-threshold MOSFETs. circuit implemented standard 0.18μm process,...

A precision bandgap reference (BGR) with high power supply ripple rejection (PSRR) and low temperature coefficient (TC) is proposed for the peripheral compensation circuitry of active-matrix organic light-emitting diode (AMOLED) displays. The PSRR enhanced by a coupling structure feedback loop start-up circuit. Furthermore, high-order nonlinear method to reduce utilizing systematic offset voltage within Measurement results BGR implemented in an industrial 0.25-μm CMOS process demonstrate TC...

This paper presents a novel 33 kHz relaxation oscillator with temperature compensation over −40–125 °C range. The voltage and current references are integrated within the proposed oscillator, resistor used to generate reference can be omitted. for comparator input is insensitive, coefficient (TC) of bias utilized compensate TC delay. compensated delay fabricated in 180-nm CMOS process an active area 0.057 mm2. measured average output frequency 96.1 ppm/°C range °C, line sensitivity 2.6%/V...

Memristor is a nonlinear circuit element which has property of memory and the similar synapse characteristic. Based on these properties, we presents memristor bridge synaptic based STDP (spike-time-dependent plasticity) learning rule an advantage that can be used as in arti cial neural network. According to advantage, combine new with other circuits networks bran-new are constructed. Firstly, three additional transistor components calculation network realized, then complete Secondly,...

A 1.02 MHz 5.72-μW 60-ppm/°C relaxation oscillator is demonstrated in a 180-nm CMOS process. The proposed simplifies the logic control circuits to save power consumption and chip area. By employing an improved delay compensation technique, has minimized sensitivity temperature variations. measured results show average frequency drift of about 60 ppm/°C below 6 μW. For supply voltage change from 1.1V 2 V, changes within only ± 1.6%.

A 0.5 V static master-slave D flip-flop (DFF) divider-by-2 is implemented with a 0.13 μm 1P8M RF-mixed signal CMOS process. Low-threshold transistors in deep-N well forward-body bias technology are used the circuit. Each of D-latch source coupled logic consists sensing and latching circuits. To increase maximum operating frequency decrease power consumption, current one half current. The circuit optimization methods described this paper. measured 6.5 GHz minimum input singled-signal amplitude 0.15 V.

This paper presents a CMOS voltage reference (CVR) with low power, high power supply ripple rejection (PSRR), and small area operating in wide temperature range. The proposed circuit contains only MOSFETs biased subthreshold region operates based on compensated ΔVTH of two different-type transistors. Implemented standard 0.18μm process, the measured CVR is 344 mV deviation 2.89 achieves an average TC 46.2ppm/°C over range from -40°C to 125°C without individual chip-by-chip trimming. PSRR -70...

An ultra-low power and offset-insensitive CMOS voltage reference circuit is presented. Due to the novel structure of employing subthreshold MOS transistors, proposed can suppress DC offset effects internal amplifier. Design considerations in optimizing area consumptions, improving supply ripple rejection (PSRR) are The implemented a 0.18μm process. Simulation results show that run with 0.8 V voltage, while consumption only 62nW, PSRR better than -43 dB over full frequency range achieved.

A subthreshold CMOS voltage reference circuit using current-mode second-order temperature compensation is proposed. Utilizing different TC-type resistors in series to reduce the required current paths, and ΔVGS of MOSFETs achieve low PTAT voltage, power area consumptions are reduced. Fabricated a 0.18-μm process, proposed achieves an untrimmed average coefficient (TC) 91ppm/ for range -40 110 over 6 samples, while consuming only 51.7nW at room temperature. The occupied active chip 0.045mm...

This paper presents a low power subthreshold CMOS voltage reference (CVR) with current loading capability. Based on the classical 2T CVR to achieve temperature coefficient (TC), sourcing PMOS is appropriately biased through local negative feedback loop. Current capability achieved without relying an output buffer. The proposed designed in standard 0.18-μm process. Simulation results show that capable of delivering 300 μA while generated Vref has less than 0.42% reduction. minimum supply 0.5...