This brief presents a fully integrated flipped-voltage-follower (FVF) based 0.96–0.9-V low-dropout regulator (LDO) with high-gain two-stage cross-coupled error amplifier (XCEA). The proposed XCEA overcomes the constraint of intrinsic gain and helps achieve better power supply rejection (PSR) load regulation. Besides, by setting supplies pass transistor EA separated unequal, efficient dropout increases different parts PSR could be measured individually. Fabricated in 28-nm bulk CMOS process,...

Abstract This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading miller of device, achieving an overall ratio 8.5. The electrical measurement shows TIA achieves 58 dBΩ up 12.7 GHz with 180-fF photodetector....

With the exponential growth of artificial intelligence systems and cloud computing, next-generation wireline transceivers are aiming for data rates 800GbE/1.6TbE, requiring 224Gb/s per lane. Potential long-reach (LR) solutions [1] include: 1) ADC/DSP-based schemes; 2) PAM-6/PAM-8/OFDM modulation or 3) PAM-4 retimers with embedded CDRs equalizers. While all above schemes based on differential signaling, there has been recent interest in single-ended schemes, such as 2D/3D interposer, UCIe,...

With the development of massive computing and AI technologies, memory interface is critical to achieve higher computational throughput. Increasing parallel-channel density an effective solution improve throughput [1]. However, due a reduced channel pitch, crosstalk between adjacent lanes becomes severe degrades signal integrity. Advanced DRAM applications, such as GDDR6x [2], have adopted PAM-4 signaling increase transmission speed; unfortunately, more sensitive crosstalk. Various TX...

The growing demand for cloud computing and artificial intelligence applications pushes wireline transceivers to higher data rates. DSP-based transmitters (TX) receivers (RX) have achieved 224Gb/s [1–2], but unfortunately consume substantial power. Furthermore, SerDes places more stringent demands on the signal integrity of passive components, such as connectors, channels, packages. In contrast, single-ended scheme may be a practical cost-effective solution First, it doubles throughput...

This paper presents a fully-integrated flipped-voltage-follower-based low-dropout regulator (LDO), with proposed high-gain two-stage cross-coupled error amplifier (XCEA). Besides, the effectiveness of bypass capacitors and diversified load is discussed. Consuming <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{170}-\boldsymbol{\mu} \mathbf{A}$</tex> quiescent current occupying area 0.019 mm <sup...

The demand for ever-increasing throughput has impelled the development of wireline TXs operating at higher data rates. In recent years, have adopted PAM-4 signaling and achieved rates more than 100Gb/s [2]–[6]. demonstrates twice bandwidth efficiency compared to NRZ. However, due different edge-transition times between middle top/bottom eyes, eyes exhibit unequal switching jitter (SWJ), leading a decrease in horizontal eye-opening deterioration signal integrity. UI-spaced FFE used only...

Micro‐LED is superior to LCD and OLED in terms of power consumption, light efficiency, contrast, response time, reliability, color gamut, lifetime, resolution viewing angle, it regarded as the most promising display technology next generation. However, there are still many technical bottlenecks that hinder development display. One important issues mass transfer. Mass transfer a aim transferring millions or even tens pixels which grown on sapphire substrates glass required for devices quickly...

This article presents a low-power 1/4-rate four-level pulse amplitude modulation (PAM4) receiver with an adaptive variable-gain rectifier (AVGR)-based decoder in 28-nm CMOS technology. The PAM4 input signal is preconditioned by continuous-time linear equalizer (CTLE) then sampled into four branches of decoders clocks. proposed AVGR-based PAM4-to-nonreturn-to-zero (NRZ) performs gain adaptation and rectification simultaneously for decoding the least significant bit (LSB). sense amplifier AVGR...

Abstract This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and reference-less clock data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ gain, 20.4-GHz −3-dB bandwidth, 12-dB DC gain tuning range. measurements the VGA’s...

This paper presents a dual-coupled single-ended (SE) receiver with crosstalk cancellation and signal reutilization (XTCR) technique in 28 nm CMOS process. The asymmetric-inductor SE to differential converter (S2D) is proposed eliminate the mismatch at its pseudo-differential outputs. conventional active extraction (AXTE) techniques are adopted one of two lanes, respectively. Compared one, AXTE can compensate for higher insertion loss without extra power consumption, improve measured...

A 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 56 Gb/s 0.78-pJ/b four pulse-amplitude modulation (PAM-4) single-ended multiple-input multiple-output (MIMO) crosstalk cancellation and signal reutilization (XTCR) receiver (RX) is investigated for medium-reach (MR) backplane communications. An XTCR scheme based on active extraction (A-XTCR) proposed to improve the...

This paper presents a reconfigurable high-linearity, energy-efficiency 112-GBaud driver with 4-level pulse amplitude modulation (PAM4) scheme in 130-nm BiCMOS. The proposed incorporates continuous-time linear equalizer (CTLE), diode-connected emitter follower, high-pass filter (HPF) and push-pull amplifier.By tuning the degenerated resistor of CTLE, can achieve variable gain from -0.6dB to 9.3dB. A wide bandwidth is realized by utilizing an capacitor. transfer 224-Gb/s PAM4 eye energy...

This paper presents a 112-Gb/s single-ended (SE) PAM-4 transceiver front-end for the reach-extension module in 130 nm SiGe BiCMOS technology. The transmitter is based on differential-to-SE driver where negative capacitance scheme introduced to extend its bandwidth. receiver features low-mismatch SE-to-differential (S2D) amplifier and an inductor-reuse continuous-time linear equalizer (CTLE). In S2D, both asymmetric reused inductor compensation techniques are implemented eliminate mismatch at...

The demand for ever-increasing throughput has impelled the swift growth of I/Os with finite areas and higher data rate per pin. To meet this demand, design passive links needs to be more complex, leading a considerable rise in hardware expenses [1]. single-ended multiple input output (SE-MIMO) scheme discussed [2], thus becomes an attractive solution, which aims transmit two (SE) signals pair tightly coupled differential channels. This halves bandwidth requirement allows 2x increase routing...

This paper presents a 28-Gb/s PAM4 fully-integrated optical receiver for short-range communication in 28-nm CMOS. incorporates an on-chip silicon photodetector, peaking-scalable trans-impedance amplifier (TIA) with the single-to-differential current buffer, two-stage variable gain amplifier, continuous-time linear equalizer, and output buffer. A P-Well/N-Well photodetector standard CMOS process less junction capacitance is employed to realize bandwidth of 4.53 GHz. The proposed TIA realizes...

This paper describes a broadband differential regulated cascode (RGC) transimpedance amplifier (TIA) designed in 130-nm SiGe process. Cross-coupled structure and two common emitter (CE) stages feedback loop are employed to reduce input impedance. The simulation results show that the proposed TIA has 46.35-dB Ω gain 35.6-GHz bandwidth (BW). Overall, it achieves clear 100-Gb/s PAM4 eye diagram. total power consumption is 84mW.

This paper presents a 160-Gb/s PAM4 optical receiver implemented in 28-nm CMOS process. The consists of an equalized inverter-based transimpedance amplifier (TIA), proposed 2-stage cascode-based single-to-differential converter (S2D), and variable gain (VGA). Inductive peaking techniques are adopted TIA S2D for broadening bandwidth. Consuming 58.79-mW power, the achieves differential conversion 76.1 dBΩ with 0.2-dB 3.2° imbalances amplitude phase, respectively.

In this work, an optical receiver (RX) with multiple peaking techniques is presented. The RX consists of a trans-impedance amplifier (TIA), continuous-time linear equalizer (CTLE), and 2-stage single-to-differential converter (S2D). Adopting the proposed RC parallel structure, TIA&#x0027;s bandwidth transition speed get improved. Moreover, techniques, including emitter degeneration, shunt-inductive T-coil peaking, are implemented for extension. With asymmetrical T-coil, S2D&#x0027;s output...