A5004439335- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Digital Filter Design and Implementation
- Neuroscience and Neural Engineering
- Physical Unclonable Functions (PUFs) and Hardware Security
- VLSI and Analog Circuit Testing
- CCD and CMOS Imaging Sensors
- Semiconductor Lasers and Optical Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Energy Harvesting in Wireless Networks
- ECG Monitoring and Analysis
- Advanced Data Compression Techniques
- Digital Media Forensic Detection
- Acoustic Wave Resonator Technologies
- Advanced Malware Detection Techniques
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Interconnection Networks and Systems
- Advanced Adaptive Filtering Techniques
- Electrostatic Discharge in Electronics
- Cell Image Analysis Techniques
- Embedded Systems Design Techniques
- Photonic and Optical Devices
Beijing Microelectronics Technology Institute
2008-2024
Xi'an Jiaotong University
2019-2024
Xidian University
2019
A voltage-controlled oscillator (VCO) with VCO-gain (KVCO) variation compensation is proposed to reduce KVCO in a current-mode logic (CML) ring by introducing cross-coupled pair capacitive degeneration that mitigates the nonlinearity of KVCO. Designed and fabricated standard 0.18-μm CMOS process, VCO can be tuned from 1.78 2.53 GHz, gain less than 14.01%, while occupying core area 0.185 × 0.081 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This article presents a space–time averaging technique that can realize instantaneous fractional frequency division, and thus, significantly reduce the quantization error in fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL). Spatial be achieved by using an array of dividers running parallel. Their different division ratios are generated...
This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise ultra-low power performance. By employing the mixed switching scheme, segmented capacitive digital-to-analog (CDAC) arrays as well synchronous data-weighted averaging (DWA) calibration block, SAR ADC can operate from 1.8 V down to 0.8 at...
This brief describes a multi-phase injection-locked ring-VCO (MPIL-RVCO) with an improved phase noise (PN), while offering inherent low-frequency output. Specifically, the MPIL-RVCO features dual oscillation loops, where RVCO substantial delay stages is integrated to reduce 1/f3 corner ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{f}_{1/{\mathrm{ f}}} ^{3}$ </tex-math></inline-formula> ), whereas...
Dynamic reconfiguration system allows us to dynamically allocate hardware resources as needed by particular applications. This paper focuses on the application of FPGA-based partial dynamic (PDRS) with configurable boundary-scan circuit (CBSC), which can be used in many different fields, especially military and aerospace fields. Generally speaking, if an important function such key encryption needs changed a PDRS operating high security system, corresponding logic need verified tested again...
A novel configurable no dead-zone digital phase detector is proposed in this paper. As an embedded SRAM employed to store configuration data, detection sensitivity of the can be controlled by data according different input frequency. Besides, avoid adopting two flip-flops and generating three state during operation. The circuit part a standard cell library easily used field programmable gate array (FPGA). PD designed betake frequency range 25 MHz 200 MHz. Simulation result for realized with...
In the surge of digital era, Metaverse, as a groundbreaking concept, has become focal point in technology sector. It is reshaping human work and life patterns, carving out new realm virtual real interaction. However, rapid development Metaverse brings along novel challenges security privacy. this multifaceted complex technological environment, data protection paramount importance. The innovative capabilities high-end devices functions owing to advanced integrated circuit technology, face...
ABSTRACT In the surge of digital era, metaverse, as a groundbreaking concept, has become focal point in technology sector. It is reshaping human work and life patterns, carving out new realm virtual real interaction. However, rapid development metaverse brings along novel challenges security privacy. this multifaceted complex technological environment, data protection paramount importance. The innovative capabilities high‐end devices functions owing to advanced integrated circuit technology,...
For Electrocardiograph (ECG) detection, the analog front-end (AFE) needs to distinguish signals with high amplitude fluctuation, in which normally an ADC 10 12 bit resolution dynamic range (DR) is required. In this paper, input-adaptive control logic proposed and implemented, enables AFE regulate gain of amplifier according input signal, 8-bit SAR reaching 67.6 dB DR near common-mode level. This design relies on powerful backend calibration process that difficulty end converted digital back...
This paper presents a power-efficient 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) in which the comparator is implemented with multi-path-input floating inverter amplifier (MPI FIA). Thanks to merits of FIA this can lower NS-SAR ADC noise and power, improve its robustness against process, voltage temperature (PVT) variation. A 12-bit...
This paper presents a highly digital technique that can significantly reduce the quantization noise of fractional- N phase-locked loops (PLLs) at all frequencies. is achieved by using an array dividers to realize spatial averaging. A fractional $\Delta \Sigma$ modulator (DSM) and data-weighted averaging (DWA) module are used generate vector division ratio for divider array. Based on this technique, 2.4-GHz frequency synthesizer implemented in 40 nm CMOS process, which with only one phase...
This brief presents a higher-order vector DEM for multibit discrete-time (DT) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol\Sigma\boldsymbol\Delta$</tex-math> </inline-formula> modulators ( Ms) to achieve higher linearity. By using the proposed filter (VF) with poles-splitting technique, root locus outside unit circle of can be eliminated, leading DAC mismatch-shaping stability will not...