A5027978089- Photonic and Optical Devices
- Electronic Packaging and Soldering Technologies
- 3D IC and TSV technologies
- Advanced Fiber Laser Technologies
- Semiconductor Lasers and Optical Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Optical Network Technologies
- Neural Networks and Reservoir Computing
- Advanced Fiber Optic Sensors
- Copper Interconnects and Reliability
- Photonic Crystals and Applications
- Hearing Impairment and Communication
- Microstructure and mechanical properties
- Hand Gesture Recognition Systems
- Semiconductor materials and devices
- Metal Forming Simulation Techniques
- Computer Graphics and Visualization Techniques
- Electrostatic Discharge in Electronics
- Remote Sensing and LiDAR Applications
- Aluminum Alloys Composites Properties
- Advanced Photonic Communication Systems
- Material Properties and Processing
- Electromagnetic Compatibility and Noise Suppression
- 3D Shape Modeling and Analysis
GlobalFoundries (United States)
2018-2023
KU Leuven
2021
Enabling cost-effective and power-efficient laser source on a silicon photonics (SiPh) platform is major goal that has been highly sought after. In the past two decades, tremendous effort made to develop various on-chip integration techniques enhance SiPh circuits with efficient light-emitting materials. Here we review our recent advancements in hybrid flip-chip of III-V lasers 300-mm monolithic platform. By leveraging advanced complementary metal oxide semiconductor (CMOS) manufacturing...
We experimentally demonstrated V-groove-based self-aligned SiN edge coupler (EC) on a monolithic CMOS-SiPh platform. <0.6/0.8 dB TE/TM SMF-EC transmission efficiency, in conjunction with <-39 back reflection and >520 mW power handling capability were achieved.
We simulated and experimentally characterized the differential group delay induced from polarization mode dispersion (PMD) of key components on a monolithic SiPh platform. Strategy for compensating PMD was introduced high-speed applications beyond 100 Gbit/s.
We report a study on moisture effect optical performance of monolithic silicon photonics technologies featuring V-grooves for self-aligned fiber attach. Chip-level hermetic sealing was achieved by implementing barrier the coupler.
We report a fiber-attach solution interfacing self-aligned, standard-cleaved fibers to monolithic photonic integrated circuits, fabricated in Globalfoundries 300-mm CMOS production facilities. Statistical yield analysis and reliability assessment were performed demonstrate the robustness of proposed solution.
Cracks at the die edge induced by dicing can grow due to chip-package interaction (CPI) and thermal cycling experienced in service. The semiconductor industry has been making major efforts prevent cracks from propagating into active area of a chip. Patterned metal structures are commonly introduced around perimeter play role as crackstop increasing fracture resistance near edge. In advance technology nodes, while introduction ultra low-k (ULK) materials reduces RC delay, it also adds CPI...
Wafer level chip scale package (WLCSP) is true with low cost by eliminating substrate. The direct chip-to-board attach through solder joints provides interconnect inductance and resistance, as well improved thermal performance. These properties make WLCSP a packaging format suited for 5G radio frequency (RF) applications where minimized size parasitics performance are critical. Due to the dissimilar between board, reliability of can be challenging. This article reports study using 45nm RFSOI...
The acceptance of Wafer Level Chip Scale Package (WLCSP) technology is significantly increasing for use in small devices such as mobile phones, wearable, RF antenna packages, and health monitor sensors. WLCSP structures can have a few thin redistribution layers (RDLs) between the chip surface printed circuit board (PCB), or interconnectors be placed direction connection to back end line (BEoL). Due high coefficient thermal expansion (CTE) mismatch silicon organic laminate, chip's level...
To enable higher computing power in a single chip, there is demand for increasing die size high performance applications advanced nodes. Due to the weak mechanical properties of low-k and ultra (ULK) dielectrics technology nodes, backend line (BEOL) stacks are more prone thermal failures, resulting increased semiconductor assembly processes reliability challenges. This further exacerbated by transition lead (Pb) based solders Pb-free (higher melting temperatures), as well copper pillar bump...
We report the hybrid flip-chip integration of III-V laser on a monolithic silicon photonics (SiPh) platform. Wafer-scale attach was demonstrated with assistance cavity Si substrate. The process accomplished through precise optical and mechanical alignment features SiPh wafer. Efficient laser-to-photonic integrated circuit (PIC) butt-coupling power up to 11 dBm achieved combination stops features. Key performance metrics such as mode hopping relative intensity noise (RIN) vs. reflectivity...
This paper details a monolithic approach to the integration of photonic systems. Polarization diverse components are fabricated in 45nm silicon-on-insulator microelectronics process flow which includes digital and RFCMOS, high performance analog mixed signal, mmWave components, electro-thermal electro-optic control elements, fiber laser attach. results single chip optical transceiver solution.
The impact of wafer level reliability TSV has been studied with respect to FEOL (Front End Line) and BEOL (Back reliability. A keep out zone (KOZ) study done varying gate length width transistor. Gate voltage (Vg) vs saturation current (Idsat) behavior indicates that there is negligible on Idsat due mechanical stress the for 5 μm KOZ both NFET PFET devices fabricated thin thick gate-oxide dielectric. Voltage Ramp Stress (VRS) Constant (CVS) tests were performed at 25°C 125°C dielectric...
This paper reports a comprehensive CPI study of large die in 5 different flip chip packaging configurations. Chip corner crack and delamination were observed temperature cycling stresses. Kerf size effect substrate studied detail. Large with wide kerf was found especially challenging for CPI, mainly due to increased energy release rate. Finite element method based modeling utilized assist the comprehension mechanism. Solution then provided resolve fails. The same test vehicle that can pass...
Wafer level chip scale package (WLCSP) is a low cost and high performing packaging format suitable for radio frequency (RF) applications where minimized size parasitics are critical. But it raises challenges to reliability. This paper reports reliability study of WLCSP using GLOBALFOUNDRIES' 45RFSOI technology. Based on comprehensive testing deep understanding the failure mechanisms, design optimizations chip, board interconnect were implemented. was significantly enhanced.
We report a hybrid flip-chip-integrated laser attach technology on monolithic SiPh platform. Efficient laser-to-PIC butt-coupling with optical power up to 11dBm was demonstrated through combination of precise mechanical stops and alignment features.
Advanced packaging is adopting more and Cu-based interconnects in addition to conventional solder-based bumps, including micro-bumps (Cu pillars with solder caps), TSVs, Cu-Cu hybrid bonding, RDLs Si bridges for lateral interconnects. Optical are also gaining traction. Heterogeneous integration of multiple chips into a package these advanced different materials poses difficult reliability challenges. This paper discusses the recent advances interconnect technologies focus on their performance.
3D cars are commonly used in self-driving systems, virtual/augmented reality, and games. However, existing car datasets either synthetic or low-quality, presenting a significant gap toward the high-quality real-world limiting their applications practical scenarios. In this paper, we propose first large-scale real dataset, termed 3DRealCar, offering three distinctive features. (1) \textbf{High-Volume}: 2,500 meticulously scanned by scanners, obtaining images point clouds with dimensions; (2)...
Isolated Sign Language Recognition (ISLR) focuses on identifying individual sign language glosses. Considering the diversity of languages across geographical regions, developing region-specific ISLR datasets is crucial for supporting communication and research. Auslan, as a specific to Australia, still lacks dedicated large-scale word-level dataset task. To fill this gap, we curate \underline{\textbf{the first}} Multi-view Multi-modal Word-Level Australian recognition dataset, dubbed...
We experimentally demonstrated V-groove-based self-aligned SiN edge coupler (EC) on a monolithic CMOS-SiPh platform. <0.6/0.8 dB TE/TM SMF-EC transmission efficiency, in conjunction with <-39 back reflection and >520 mW power handling capability were achieved.
We simulated and experimentally characterized the differential group delay induced from polarization mode dispersion (PMD) of key components on a monolithic SiPh platform. Strategy for compensating PMD was introduced high-speed applications beyond 100 Gbit/s.
We report a study on moisture effect optical performance of monolithic silicon photonics technologies featuring V-grooves for self-aligned fiber attach. Chip-level hermetic sealing was achieved by implementing barrier the coupler.