A5003065581- Interconnection Networks and Systems
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Cryptographic Implementations and Security
- Physical Unclonable Functions (PUFs) and Hardware Security
- Superconducting and THz Device Technology
- Chaos-based Image/Signal Encryption
- Advanced Memory and Neural Computing
- Physics of Superconductivity and Magnetism
- Power Systems and Technologies
- Smart Grid Energy Management
- Security in Wireless Sensor Networks
- Radiation Effects in Electronics
- Dark Matter and Cosmic Phenomena
- Organic Chemistry Cycloaddition Reactions
- Advanced Synthetic Organic Chemistry
- Radio Frequency Integrated Circuit Design
- Synthesis of Organic Compounds
- Regional Economic and Spatial Analysis
- Synthetic Organic Chemistry Methods
- Superconducting Materials and Applications
- Graphene research and applications
- VLSI and Analog Circuit Testing
- Mobile Ad Hoc Networks
- Advanced Computational Techniques and Applications
State Grid Corporation of China (China)
2022-2024
The University of Sydney
2023
Queen's University Belfast
2009-2012
University of British Columbia
1988-2006
Zhejiang University
2005
Beijing City University
2000
The energy consumption is a key design criterion for the routing protocols in wireless sensor networks. Some of conventional single path schemes may not be optimal to maximize network lifetime and connectivity. In this paper, we propose distributed, scalable localized multipath search protocol discover multiple node-disjoint paths between sink source nodes. We also load balancing algorithm distribute traffic over discovered. compare our proposed scheme with directed diffusion, transmission,...
A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored FPGA, is presented. This has been designed to be scalable at system level fully exploit the characteristics constraints of FPGA based systems, rather than custom ASIC technology. key feature that it achieves a low packet propagation latency only two cycles per hop including both pipeline delay link traversal - significant enhancement over existing designs whilst being very competitive in terms...
Aggressive MOS transistor size scaling substantially increase the probability of faults in NoC links due to manufacturing defects, process variations, and chip wire-out effects. Strategies have been proposed tolerate faulty wires by replacing them with spare ones or partially using defective links. However, these strategies either suffer from high area power overheads, significantly average network latency. In this paper, we propose a novel flit serialization method, which divides flits into...
This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss interlock NoC allocator, which is caused by lock mechanism priority updating between local and global arbiters. Architectures implementations three interlock-free allocators are presented in detail. Their cost, critical path, as well networklevel performance demonstrated based on 65-nm standard cell technology.
A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The enables high performance cost effective VC NoC on-chip system interconnects to deployed on FPGA.
Sudden dramatic rises in electricity prices, known as "price spikes", are ubiquitous spot markets worldwide. These price spikes often cluster. Energy retailers many countries, including Australia, purchase an unregulated market and sell it to consumers at a heavily regulated price. As result, the occurrence clustering of is particularly hazardous for retailers, effective modelling forecasting these foremost importance risk management. This paper uses data-dependent two-regime threshold...
A number of simple performance measurements on disk speed, CPU, memory and network throughput were done a dual ARM Cortex-A7 machine running Linux inside Xen virtual that communicate with the outside through fronted-driver backend-driver. The average overhead is between 3 7 percent when host lightly loaded (running only system software necessary xenstored demon so on).
FPGA based soft-processors are an attractive approach for embedded system engineering. Multithreading is proposed as the method to manage long latency events that caused by I/O, off-chip memory and other shared resource accesses. However, most of earlier multi-threaded were on conventional FPMT CGMT architectures, which fall short several reasons. In this paper, we propose a novel multithreading architecture eliminates thread switch penalty, while maintaining single performance.
Attackers can reveal the secret key stored in an electronic cryptographic device from instantaneous power consumption using statistical analysis. The technique used to attack such devices by monitoring is called Differential Power Analysis (DPA). To date, two variants of basic DPA have been developed, which are Correlation (CPA) and Frequency-based (DFA). In this research DPA, CPA DFA attacks performed on Application Specific Integrated Circuit (ASIC) implementation Advanced Encryption...
The secret key stored in a cryptographic device can be revealed from the power consumption using statistical analysis technique known as differential (DPA). However, DPA attacks are sensitive to measurement misalignments samples that reduce dependency between and data. A countermeasure increases this misalignment by inserting random delays operations, delay insertion, was shown previous research effective against on hardware implementations. frequency-based attack (DFBA) is involves...
Electronic cryptographic devices can be attacked by monitoring physical characteristics released from their circuits, such as power consumption and electromagnetic emanation. These techniques are known Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is one of the most effective SCAs, which reveal secret key dependency between device processed data. This paper proposes a DPA resistant solution for FPGA implementations Advanced Encryption Standard (AES), combines two...
The HaL SPARC64 Processor, the first 64-bit SPARC-V9 architecture implementation, uses several techniques to ensure a high degree of system reliability, error detection, and recovery. CPU multi-chip module processor has superscalar, speculative issue unit, an out-of-order execution datapath. These two components complicate maintenance precise state in event errors. By exploiting architectural features, micro-architecture for execution, maintains exceptions errors, logs reports facilitates...
Scalability and efficiency of on-chip communication emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number cores. Networks-on-Chip (NoC) is widely accepted as the next generation scheme scale MPSoC. The increase complexity requires fast accurate system-level modeling techniques rapid verification MPSoCs. However, existing methods limited in delivering essentials timing...
Security devices are vulnerable to differential power analysis (DPA) that reveals the key by monitoring consumption of circuits. In this paper, we present first DPA attack against an FPGA implementation camellia encryption algorithm with all sizes and evaluate resistance algorithm. The Camellia cryptographic involves several different key-dependent intermediate operations including S-Box operations. previous research, it was believed is stronger than AES due additional Whitening phase...
With the over-provisioned routing resource on FPGA, topology choice for NoC implementation FPGA is more flexible than ASIC. However, it well understood that global wire impacts performance of because routed by using fixed fabric. An important question arises is: will benefit diameter reduction a highly connective outweigh impact routing? To answer this question, we investigate based packet switched implementations with different sizes and topologies, quantitatively measure to each these...
Blocked multithreading architecture can overcome several drawbacks of interleaved architecture. However, it introduces context switching penalty which degrades the overall performance. We propose an advanced static blocked that avoids while maintains single thread An analytical method for performance evaluation is presented, followed by simulation results demonstrating advantage proposed in terms its
Abstract ChemInform is a weekly Abstracting Service, delivering concise information at glance that was extracted from about 100 leading journals. To access of an article which published elsewhere, please select “Full Text” option. The original trackable via the “References”