The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput up to 530 Mpixels/s greatly challenges design real-time video decoder VLSI with extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique partial MB reordering scheme are proposed save access QFHD chip. Besides, pipelining parallelization techniques such as...

Ultra high definition television (UHDTV) imposes extremely throughput requirement on video encoders based High Efficiency Video Coding (H.265/HEVC) and Advanced (H.264/AVC) standards. Context-adaptive binary arithmetic coding (CABAC) is the entropy component of these In very-large-scale integration implementation, CABAC has known difficulties in being effectively pipelined parallelized, due to critical bin-to-bin data dependencies its algorithm. This paper addresses encoding for UHDTV...

3840 × 2160 and 7680 4320 UHDTV formats deliver remarkably enhanced visual experience relative to high definition but in the meanwhile involve huge complexity memory bandwidth requirements video encoding. Especially, enlarged motion distances of lead additional difficulties implementation estimation, which is originally most critical bottleneck an encoder. This paper presents a estimation processor design for H.264/AVC. A test chip implemented 40 nm CMOS. With algorithm architecture...

In recent years, the layered image compression is demonstrated to be a promising direction, which encodes compact representation of input and apply an up-sampling network reconstruct image. To further improve quality reconstructed image, some works transmit semantic segment together with compressed data. Consequently, ratio also decreased because extra bits are required for transmitting segment. solve this problem, we propose new framework encoder-decoder matched segmentation (EDMS). And...

8K Ultra HD is being promoted as the next-generation digital video format. From a communication channel perspective, latest high-efficiency coding standard (H.265/HEVC) greatly enhances feasibility of by doubling compression ratio. Implementation such codecs challenge, owing to ultra-high throughput requirements and increased complexity per pixel. The former corresponds up 10b/pixel, 7680×4320pixels/frame 120fps - 80× larger than 1080p HD. latter comes from new features HEVC relative its...

8K ultra-HD is being promoted as the next-generation video specification. While High Efficiency Video Coding (HEVC) standard greatly enhances feasibility of with a doubled compression ratio, its implementation challenge, owing to ultrahigh-throughput requirements and increased complexity per pixel. The latter comes from new features HEVC. At system level, most challenging them enlarged highly variable-size coding/prediction/transform units, which significantly increase requirement for...

Convolutional neural networks(CNNs) are often over-parameterized and cannot apply to existing resource-limited artificial intelligence(AI) devices. Some methods proposed model compress the CNNs, but these data-driven unable when lacking data. To solve this problem, in paper, we propose a data-free compression acceleration method based on generative adversarial networks network pruning(named DFNP), which can train compact only needs pre-trained network. The DFNP consists of source network,...

Compressive Sensing (CS) has emerged as a transformative technique in image compression, offering innovative solutions to challenges efficient signal representation and acquisition. This paper provides comprehensive exploration of the key components within domain CS applied video compression. We delve into fundamental principles CS, highlighting its ability efficiently capture represent sparse signals. The sampling strategies employed compression applications are examined, emphasizing role...

8K×4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way being the next digital TV standard. In addition, advanced 3DTV specifications involving large number of camera views are targeted by emerging applications such as free-viewpoint (FTV). This paper presents single-chip design that supports real-time H.264 decoding SHV or up 32 HD views. The chip involved 3 key challenges: 1) Data dependencies video coding algorithms restrict...

Computer vision applications are rapidly gaining popularity in embedded systems, which typically involve a difficult tradeoff between performance and energy consumption under constraint of real-time processing throughput. Recently, hardware (FPGA ASIC-based) implementations have emerged, significantly improves the efficiency computation. These implementations, however, often intensive memory traffic that retains significant portion at system level. To address this issue, we first researchers...

Compressive Sensing (CS) surpasses the limitations of sampling theorem by reducing signal dimensions during sampling. Recent works integrate measurement coding into CS to enhance compression ratio. However, these significantly decrease image quality, and both encoding decoding become time-consuming. This paper proposes a based Image Codec with Partial Pre-calculation (CSCP) solve issues. The CSCP separates original reconstruction procedure two parts: reconstructing frequency domain data...

An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth reduced results 58% power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving 54%.

This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%~34% with proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both HEVC H.264/AVC formats can be supported our applying dualstandard binarization design. The CABAC silicon proven in 65nm video encoder chip. It delivers...

Motion compensated prediction is one of the essential methods to reduce temporal redundancy in inter coding. The target motion predict current frame from list reference frames. Recent video coding standards commonly use interpolation filters obtain sub-pixel for best matching block located fractional position frame. However, fixed are not flexible adapt variety natural contents. Inspired by success Convolutional Neural Network (CNN) super-resolution, we propose CNN-based Luminance (Luma) and...

The increase of video content and resolution drive more exploration compression techniques recently. Meanwhile, learning-based is receiving much attention over the past few years because its adaptivity parallelable computation. Although several promising reports were introduced, there no breakthrough work that can further go out research area. In this work, we provide an up-to-date overview milestones. particular, idea recent works on modules for conventional codec adaption end-to-end are...

The complexity of deep neural network models (DNNs) severely limits their application on devices with limited computing and storage resources. Knowledge distillation (KD) is an attractive model compression technology that can effectively alleviate this problem. Multi-teacher knowledge (MKD) aims to leverage the valuable diverse distilled by multiple teacher networks improve performance student network. Existing approaches typically rely simple methods such as averaging prediction logits or...

In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support QFHD@60fps sequences at less than 100MHz. 4 edge filters organized 2 groups simultaneously processing vertical horizontal edges are applied enhance its throughput. While parallelism increases, pipeline hazards arise owing the latency of data dependency algorithm. To solve problem, zig-zag schedule eliminate bubbles. Data path then...

An H.264/AVC intra-frame video encoder is implemented in 65 nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991 Mpixels/s for 7680×4320 p 60 fps video, 9.4× to 32× faster than previous designs. The also incorporates a 1.41 Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption achieved the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2 mW at 0.8 V 9 MHz.

Motion estimation and motion compensation in HEVC similar video codecs involve huge memory traffic storing loading reference frames. The resulting power composes a significant portion of system energy consumption. This paper presents reduction framework that losslessly compresses decompresses frames on-the-fly. We first present the architecture supports random access frame data compressed variable ratios. latest recompression algorithms corresponding VLSI implementation are also introduced....