The significant part of every digital signal processing (DSP) application is a multiplier.This work presents the highperformance 4x4 and 8x8 Vedic multiplier designed utilizing scalable adder compressor architectures.Several 8-bit designs, namely CPL, GDI 1, Scalable full adders, are implemented to establish superiority adder, which used for implementation.The proposed Multiplier architecture, comprises half chain 3-2 compressors, 4-2 compressors.The design metrics compared existing Binary,...

The technique of body biasing has achieved great success in modern IC design as it, is possible to alter the threshold voltage MOS transistor so that device leakage and timing performance can be improved. In this paper a Schmitt trigger circuit been designed using four types bias techniques. proposed circuits were simulated SPICE 180nm CMOS technology parameters. A comparative study all terms lower upper voltages, noise margins power dissipation done specific applications for each suggested.

Miniaturization has been a constant challenge to meet the demands of high performance, density, low power and voltage complex devices. is main driving force for migration from micro electronic device structures Nano structures. Planar CMOS scaling delivering better performance & devices at each cutting edge technology node more than three decades. Now, facing crucial limitations some show stoppers are affecting bulk scaling. So, semiconductor industry witnessing phase-out with introduction...

In this study, an approach to implement wide word-length adders is presented by proposing a hybrid 4-bit carry generator. The proposed generator uses combination of Carry Look-Ahead (CLA) and Ripple (RC) styles. Utilization RC style in the first 3-bits aims reduce transistor count along with power consumption. On other hand, CLA method used 4th bit ensure speed. Also, for novel approach, which inverted Propagate (Pi‾) - Generate (Gi‾) circuits rather than using conventional ones. Performance...

Measurements of the linearity a guard-ring, three-terminal capacitance transducer have been made with precision and effects slight non-parallelism electrodes order minutes arc observed for small electrode separations. Although results can be explained by classical theory large separations (g>r/75, where g is separation r radius central electrode) no such agreement obtained data.

A detailed and thorough study has been carried out to realize the working of our proposed device which is a Germanium (Ge) pocket based Tunnel Field Effect Transistor (TFET). The employs germanium near source channel junction double-gate TFET. Germanium, being low bandgap material, increases transmission rate electrons at tunneling hence improves ON state performance device. TFET also uses dual oxide, with hafnium oxide (HfO2) side silicon dioxide (SiO <inf...

With excessive scaling in the VLSI industry, Carbon Nanotube Field Effect Transistor(CNTFET) is emerging as a potential replacement to traditional MOSFET technology.XOR gate an essential component various digital logic circuit designs.Therefore it crucial devise high performing XOR and XOR-XNOR increase overall efficiency of based circuits.This paper investigates performance several designs individual gates well simultaneous circuits for different applications.The implemented have been...

In this paper, we propose and simulate a Germanium Source-Double Gate Tunnel-field Effect Transistor with metallic drain (GS-DGTFET-MD). The use of source metal silicide has significantly improved the ON current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) ambipolar suppression in proposed device comparison to conventional DGTFET. A two dimensional (2D) calibrated simulation study revealed ~3 orders improvement I ~10 reduction...

Abstract The observed phenomenon of slip between the layers a flowing slurry is modelled mathematically by finite‐element‐based numerical technique. This technique enables us to quantify variables such as velocity and shear stress distribution at interlayer boundary pressure drop within flow domain.

In the recent era, voltage reduction procedure is gaining most attention for achieving minimum energy consumption. Full adder primary computational arithmetic block in numerous of computing executions and hence critical component ALU.Various existing full adders proposed literature fail to accomplish low power delay product (PDP) lacks driving strength when used chainsstructure.In this paper two new hybrid have been proposedwith an aim achieve PDP.Further proposesripple carry (RCA)...

This paper proposes a novel circuit design of Ternary Full Adder (TFA) using proposed 3:1 multiplexer (3:1 TMUX) and Half (THA). research focuses on achieving low power consumption propagation latency in these circuits. The is compared with existing circuits demonstrates superior performance based their metrics. analysis simulations were conducted Cadence Virtuoso environment at 90 nm technology. simulation results indicate that the designs outperform other terms power-delay product (PDP)...

This paper proposes a novel circuit design of two Ternary Half Subtractor (THS) and Full (TFS) using Double pass transistor logic (DPL). The proposed THS is implemented by basic ternary inverters DPL implementation Difference Borrow circuits. TFS uses 1:3 decoder 3:1 multiplexers approach focuses on achieving low power consumption propagation delay. circuits are compared with existing demonstrate superior performance based their metrics. analysis simulations were conducted Cadence Virtuoso...

This paper delineates a simulated neural signal amplifier with very high gain and enhanced supply rejection along low noise operation. We describe micro-power complementary metal-oxide-semiconductor (CMOS) design. The comprises of two stages at the input juncture, differential pair is used to attain an optimum input-referred noise. outlined in typical 180-nm CMOS process using cadence tool. design yields midband 70.0 dB 4.33 µVrms frequency from 320 mHz 9.0 kHz selected as - 3 bandwidth...