A5082452997- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Energy Harvesting in Wireless Networks
- Electromagnetic Compatibility and Noise Suppression
- Microwave Engineering and Waveguides
- Neuroscience and Neural Engineering
- Electrostatic Discharge in Electronics
- Advanced Power Amplifier Design
- Acoustic Wave Resonator Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- CCD and CMOS Imaging Sensors
- Wireless Power Transfer Systems
- Advanced Memory and Neural Computing
- Innovative Energy Harvesting Technologies
- Sensor Technology and Measurement Systems
- Advanced DC-DC Converters
- EEG and Brain-Computer Interfaces
- Physical Unclonable Functions (PUFs) and Hardware Security
- Advanced MEMS and NEMS Technologies
- Experimental Learning in Engineering
- VLSI and FPGA Design Techniques
Northeastern University
2016-2025
Universidad del Noreste
2015-2022
Boston University
2011-2021
State of The Art
2020
Dana (United States)
2012-2017
Analog Devices (United States)
2010-2014
Texas A&M University
2006-2014
Abstract Ultra-compact wireless implantable medical devices are in great demand for healthcare applications, particular neural recording and stimulation. Current technologies based on miniaturized micro-coils suffer from low power transfer efficiency (PTE) not always compliant with the specific absorption rate imposed by Federal Communications Commission. Moreover, current reliant differential of voltage or across space require direct contact between electrode tissue. Here, we show an...
This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable system-on-chip (SoC) applications while maintaining capability reduce high-frequency noise. The paths of noise output are analyzed, and cancellation circuit developed. PSR performance improved by using replica that tracks main under process-voltage-temperature variations all operating conditions. effectiveness enhancement...
A major obstacle during the design of brain- computer interfaces is unavailability a neural implantable device that μ-scale in size and wireless, self-powered, long-lasting. The current state-of-the-art devices suffer from various limitations. Electromagnetic-based wireless are big because their large antenna, which must be larger than one-tenth wavelength operational frequency. Ultrasound-based devices, addition to low data rate, have massive loss skull need an intermediate electromagnetic...
This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. has been designed to operate over very wide temperature range from -40 °C 150 °C. Its output voltage is 1.16 V 3.3-V supply voltage. A multi-section curvature method alleviates the error bipolar junction transistor's base-emitter nonlinear dependence on temperature. The contains two operational amplifiers that are utilized generate...
An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with transconductance-capacitor (G<sub>m</sub>-C) filter. The technique utilizes two matched OTAs to cancel output harmonics, creating robust architecture. Compensation process variations frequency-dependent distortion based on Volterra series analysis achieved by employing delay equalization on-chip programmable resistors. OTA design...
This brief introduces a digital calibration technique to boost the input impedance of instrumentation amplifiers (IAs) with digitally tunable impedance. The employs two machine learning-driven optimization algorithms, genetic algorithm (GA) and particle swarm (PSO) algorithm, efficiently control integrated capacitor banks within IA for determination optimal These algorithms offer significant time reduction compared an exhaustive search, reducing by factor over 106 (with four 9-bit words)...
We report new high quality factor (Q) integrated GHz magnetic inductors based on solenoid structures with FeGaB/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">${\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> multilayer films, which show significantly enhanced inductance and at frequencies over their air core counterparts. These an excellent high-frequency performance a wide operation frequency range...
This paper demonstrates an input impedance boosting method that was developed for long-term monitoring of electroencephalography signals. An instrumentation amplifier designed with a negative capacitance generation feedback (NCGFB) technique to cancel the adverse effects capacitances from electrode cables and printed circuit boards. The NCGFB boosts measured below 40 MΩ above 500 MQ at 50 Hz when equivalent inputs is up 150 pF. prototype chip includes automatic calibration system adaptively...
This paper introduces a continuous-time low-pass sigma-delta modulator operating with seven-phase 400 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex> </formula> MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator complementary injection-locked frequency divider are utilized...
Abstract Massive deployments of wireless sensor nodes (WSNs) that continuously detect physical, biological or chemical parameters are needed to truly benefit from the unprecedented possibilities opened by Internet-of-Things (IoT). Just recently, new sensors with higher sensitivities have been demonstrated leveraging advanced on-chip designs and microfabrication processes. Yet, WSNs using such require energy transmit sensed information. Consequently, they either contain batteries need be...
A magnetoelectric antenna (ME) can exhibit the dual capabilities of wireless energy harvesting and sensing at different frequencies. In this article, a behavioral circuit model for hybrid ME antennas is described to emulate radio frequency (RF) operations during simulations. The work interfaced with CMOS harvester chip towards goal developing communication link fully integrated implantable devices. One role system receive pulse-modulated power from nearby transmitter, another sense transmit...
In this paper, a practical current injection based built-in test (BIT) technique for impedance-matched RF low-noise amplifiers (LNAs) is proposed. A generation circuit injects the at gate of LNA; approach has advantage that matching network not affected by circuitry. The can be used without design changes to measure voltage gain during on-wafer and S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> final in presence inductance package...
The focus in this paper is on the extraction of RF circuit performance characteristics from dc output an on-chip temperature sensor. Any input signal can be applied to excite under examination because only dissipated power levels are measured, which makes approach attractive for online thermal monitoring and built-in test scenarios. A fully differential sensor topology introduced that has been specifically designed proposed method by constructing it with a wide dynamic range, programmable...
This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding subranging two-step pipelined successive approximation ADCs) are described with particular focus on their suitability the construction of power-efficient hybrid ADCs. The overview includes discussions channel offsets gain mismatches, timing skews, bandwidth other considerations design. As an example, a architecture...
A new method is discussed for the systematic synthesis, design and performance optimization of varactor-based parametric frequency dividers (PFDs) exhibiting an ultra-low power threshold ($P_{th}$). For first time, it analytically shown that $P_{th}$-value exhibited by any PFD can always be expressed as explicit closed-form function different impedances forming its network. Such a unique unexplored property permits to rely on linear models, during optimization. The validity our analytical...
The fast Fourier transform (FFT) algorithm is widely used as a standard tool to carry out spectral analysis because of its computational efficiency. However, the presence multiple tones frequently requires fine frequency resolution achieve sufficient accuracy, which imposes use large number FFT points that results in area and power overheads. In this paper, an method proposed for on-chip multi-tone signals with particular harmonic intermodulation components. This accurate approach based on...
This paper describes a linearization method to enhance the third-order distortion performance of subthreshold common-source cascode low-noise amplifier (LNA) without extra power consumption by using passive components. An inductor between gate transistor and supply in combination with digitally programmable capacitor drain enable improve intermodulation intercept point (IIP3) LNA. The theoretical mechanisms that underlie linearity improvement are analyzed comprehensively under consideration...
This work report new integrated high quality factor (Q) GHz magnetic transformers based on solenoid structures with FeGaB/Al2O3 multilayer films. These show excellent high-frequency performance a wide operation frequency range of 0.5–5 GHz, in which primary, secondary, and mutual inductances are flat, the peak can reach around 14 at 1.2 GHz. High coupling low insertion loss also demonstrated. novel Q great promise for applications radio circuits.
This paper presents a fully integrated RF energy harvester (EH) with 30% end-to-end power harvesting efficiency (PHE) and supports high output voltage operation, up to 9.3V, 1.07 GHz input under the electrode model for neural applications. The EH is composed of novel 10-stage self-biased gate (SBG) rectifier an on-chip matching network. SBG topology elevates gate-bias transistors in non-linear manner enable higher conductivity. design also achieves >20% PHE range 12-dB. was fabricated 65 nm...
This paper introduces a differential temperature sensor that is tailored for on-chip thermal profiling to monitor the power dissipation of circuits. Chopper stabilization and analog offset calibration are integrated within circuit design suppress low-frequency flicker noise DC offsets, respectively. A prototype chip proposed with test heat sources was fabricated in standard 65-nm CMOS process. measured sensitivity 21.1 mV/μW achieved over dynamic range 34 μW, which highest reported an...
This paper presents two approaches to characterize RF circuits with built-in differential temperature measurements, namely the homodyne and heterodyne methods. Both non-invasive methods are analyzed theoretically discussed regard respective trade-offs associated practical off-chip methodologies as well on-chip measurement scenarios. Strategies defined extract center frequency 1 dB compression point of a narrow-band LNA operating around GHz. The proposed techniques experimentally demonstrated...
This paper presents a subthreshold cascode low-noise amplifier (LNA) with inductive source degeneration and third-order linearity enhancement. The LNA architecture includes an inductor capacitor at the gate of transistor for partial cancellation distortion components. design method enables intermodulation intercept point (IIP3) 1dB compression (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) improvements 4.8-11.2 dB 7.1-11.6...
An 8-bit 1-GS/s hybrid analog-to-digital converter (ADC) for high-speed low-power applications is introduced. It has a subranging architecture with 3-bit flash ADC as first stage and 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) second stage. In each channel, merged sample-and-hold capacitive digital-to-analog (SHDAC) performs the sampling residue generation operation. The effects of parasitic capacitances on SHDAC linearity are analyzed, correction...