A5011279100- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- EEG and Brain-Computer Interfaces
- Sensor Technology and Measurement Systems
- Herpesvirus Infections and Treatments
- Catalysis and Hydrodesulfurization Studies
- Hepatitis C virus research
- Advancements in Semiconductor Devices and Circuit Design
- Power Systems Fault Detection
- Advancements in PLL and VCO Technologies
- Antibiotics Pharmacokinetics and Efficacy
- Neuroscience and Neural Engineering
- HVDC Systems and Fault Protection
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Photolithography Techniques
- Hydrogen Storage and Materials
- Advanced Photonic Communication Systems
- Electrical Fault Detection and Protection
- Advanced Memory and Neural Computing
- Optical Network Technologies
- VLSI and Analog Circuit Testing
- Electrocatalysts for Energy Conversion
Northeastern University
2019-2025
Helwan University
2024
Cairo University
2004-2016
This brief introduces a digital calibration technique to boost the input impedance of instrumentation amplifiers (IAs) with digitally tunable impedance. The employs two machine learning-driven optimization algorithms, genetic algorithm (GA) and particle swarm (PSO) algorithm, efficiently control integrated capacitor banks within IA for determination optimal These algorithms offer significant time reduction compared an exhaustive search, reducing by factor over 106 (with four 9-bit words)...
This article presents a design approach for the modeling and simulation of ultralow power (ULP) analog computing machine learning (ML) circuits seizure detection using electroencephalography (EEG) signals in wearable health monitoring applications. In this article, we describe new system technique to associate consumption, noise, linearity, other critical performance parameters with classification accuracy given ML network, which allows realize optimized hardware implementation based on...
This brief presents an ultra-low power received signal strength indicator (RSSI) amplifier circuit that can be used to detect seizures through feature extraction from electroencephalography (EEG) signals. The RSSI-based method provides a low-power area-efficient solution for analog computing based seizure detection hardware. A 6-stage RSSI was designed in 65nm CMOS technology cover the dynamic range of EEG signals with area <inline-formula> <tex-math notation="LaTeX">${266\mu m \times 531...
A symmetric chopper instrumentation amplifier architecture with two identical 8-bit digitally programmable capacitor banks and online digital calibration block are presented. Designed for long-term brain signal monitoring applications, the feedback generate negative capacitance to cancel input from electrode cables boost impedance above 2 GΩ at 10 Hz. These controlled by an automatic background unit that includes oscillation prevention scheme ensure stable operation. chopping technique is...
The Cairo University SPARC (CUSPARC) processor is an IP embedded based on V8 ISA standard. It fully developed at and the first Egyptian processor. CUSPARC was implemented several FPGA ASIC platforms. Its version (CUSPARC V1) Si in 2010 using IBM 0.13μm CMOS 8RF-DM process. This paper reports design, fabrication testing of enhanced CUSPARC, labelled V2. V2 augmented with ADPLL, a hardware multiplier, four JTAG scan chains.