Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, relatively current flowing through an MTJ always required by most of the switching mechanisms, which results in electric field significant self-heating effect. This may lead dielectric breakdown ultrathin (~1 nm) oxide barrier cause functional errors hybrid CMOS/MTJ paper analyzes...

In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes normally-off electronics will need to meet constraints in speed, energy robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) scaling MTJ NV-LIM is evaluated FD-SOI 28 nm node. order overcome V...

The Internet of Things (IoTs) relies on efficient node memories to process data among sensors, cloud and RF front-end. Both mainstream emerging have been developed achieve this energy efficiency target. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile memory (NVM) has demonstrated great performance in terms zero standby power, switching power efficiency, infinite endurance high density. However, it still a big gap; e.g., dynamic write energy, large latency, yield...

Nanoelectronic systems are now more and prone to faults defects, permanent or transient. Redundancy techniques implemented widely increase the reliability, especially TMR - Triple Modular Redundancy. However, many researchers assume that voter is perfect this may not be true. This paper proposes a simple but effective fault-tolerant circuit which reliable less expensive. Experimental results demonstrate its improvement over former structures.

A novel low-power nonvolatile magnetic flip-flop is introduced in this paper. The perpendicular anisotropy spin torque transfer tunnel junction (STT-MTJ) used to design the hybrid MTJ/CMOS circuit, which implemented with 28-nm high-κ metal gate and planar ultrathin body buried oxide fully depleted silicon on insulator technology. proposed structure named SA-MFF shares a sensing amplifier for normal mode data mode. modified latch at output stage improves latency. symmetrical, provides an...

This paper presents a reliability analysis algorithm that can be integrated in the design flow of logic circuits. Based on four state representation signal probabilities, and propagation this probabilities along cells circuit, circuit directly obtained. The use rises well known problem signals correlation, we present some relaxing conditions allow tradeoffs between accuracy execution time algorithm. main advantages proposed methodology are its simplicity straightforward application, allowing...

Defects as well soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce cost-aware methodology for selective hardening of combinational logic cells. The is based on the SPRA algorithm calculating logical masking, it capable automatically perform trade-off between improvements associated costs, providing list most...

Reliability analysis of digital circuits is becoming an important feature in the design process nanoscale systems. Understanding relations between circuit structure and its reliability allows designer to implement some tradeoffs that can improve resulting design. This work presents a probabilistic model computes combinational logic relating single multiple faults. The methodology targeted (but not limited) generated by synthesis tools, standard cell based implementation. To validate proposed...

The reliability of integrated circuits has become an unavoidable subject in the nanoscale era. susceptibility combinational logic to faults is increasing interest, and fast accurate methods are necessary take into account earlier design process. As scale nanometer dimensions, probability occurrence multiple simultaneous becomes higher cannot be neglected anymore. In this work, a signal analysis (SPRA) algorithm presented, allowing evaluation relating faults.

Stochastic Computing (SC) with random bit streams has been used to replace binary radix encoding. SC-based logic cicuits take advantage of area minimization, fast and accurate operation inherent fault tolerance. In this paper, the stochastic characteristics in Spin Torque Transfer Magnetic Tunnel Junction (STT-MTJ) bring on an innovative number generator (SNM) circuit. The hybrid MOS-MTJ process allows design a 4T1M structure SNM 1.98μm∗1.46μm layout area, using 28 nm ultra thin body buried...

In this work, we deal with the design and implementation of a decimation filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes steps tradeoffs concerning hardware implementation. GSM DECT standards specifications are met by proposed filtering cascade structure. processes six-bit data stream input from fourth-order sigma-delta modulator has been prototyped field-programmable gate array device.

In this paper, we present the heavy-ion radiation test results for a 7-stage SPARC micro-processor. Special software handlers enabled fine grained classification of types crashes. The measured crash cross sections are compared with those predicted by fault injection simulation.

Emerging memories have been developed to achieve energy efficiency target in the Internet of Things era. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile (NV) memory has demonstrated attractive performance because zero standby power, reduced switching infinite endurance, and high density. Meanwhile, hybrid STT-MTJ/CMOS integration is a promising solution overcome bottleneck dynamic leakage power dissipation. In this paper, ultralow methodologies are at device circuit...

The planar ultrathin body and buried oxide fully depleted silicon-on-insulator (FDSOI) technology is one of the proper candidates to replace bulk CMOS due its high volume, low cost, lower power. In this paper, we investigate performance hybrid magnetic-MOS non-volatile (NV) magnetic flip-flops (MFFs) in FDSOI technology. NV-MFF parameters, e.g., active power, leakage sensing delay, are optimized with selected design vectors: supply voltage (V <sub...