- Graphene research and applications
- Low-power high-performance VLSI design
- 3D IC and TSV technologies
- Carbon Nanotubes in Composites
- Semiconductor materials and devices
- Electronic Packaging and Soldering Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Electromagnetic Compatibility and Noise Suppression
- Gas Sensing Nanomaterials and Sensors
- Additive Manufacturing and 3D Printing Technologies
- Semiconductor materials and interfaces
- Ferroelectric and Negative Capacitance Devices
- Quantum-Dot Cellular Automata
- Advanced Memory and Neural Computing
- VLSI and FPGA Design Techniques
- Copper Interconnects and Reliability
- Interconnection Networks and Systems
- Crystallization and Solubility Studies
- Physical Unclonable Functions (PUFs) and Hardware Security
- Integrated Circuits and Semiconductor Failure Analysis
- X-ray Diffraction in Crystallography
- Graphene and Nanomaterials Applications
- Nanotechnology research and applications
- Catalytic Processes in Materials Science
- Analog and Mixed-Signal Circuit Design
International Institute of Information Technology
2017-2024
International Institute of Information Technology
2019-2020
Fourth Paradigm Institute
2020
Indian Institute of Information Technology, Nagpur
2019
Techno India University
2016
Indian Institute of Technology Roorkee
2011-2015
All India Council for Technical Education
2014
Dayalbagh Educational Institute
2014
Deenbandhu Chhotu Ram University of Science and Technology
2014
Indian Institute of Technology Kanpur
2010
Mixed carbon nanotube bundles (MCBs) are considered to be highly potential interconnect solutions in the current nanoscale regime. Different MCBs with random and spatial arrangements proposed based on placements of single- multiwalled nanotubes (CNTs) (SWNTs MWNTs) a bundle. Propagation delay dynamic crosstalk performances analyzed using modified equivalent single conductor model MCB topologies. Encouragingly, significant reduction propagation is observed for arrangement an wherein MWNTs...
Multilayer graphene nanoribbons (MLGNRs) have potentially provided attractive solutions in an intensely growing researched area of interconnects. However, for MLGNR interconnects, the doping is inevitable since conductivity neutral much lower than even Cu. Therefore, a doped can exhibits smaller resistance comparison to Cu wires. This paper analyzes and compares power, delay, bandwidth performance using equivalent single conductor model. For similar dimensions, overall delay power...
Multiwalled carbon nanotube (MWCNT) and bundled single-walled (SWCNT) interconnect have provided potentially attractive solution in current deep submicrometer nanoscale technology. This letter presents a comparative analysis between the MWCNT SWCNT at different global lengths terms of crosstalk-induced time delay area by using three-line-bus architecture. Each line bus architecture is replaced RLC models bundled-SWCNT interconnects. The predicted middle (victim) when other two lines...
This reported research analyses and compares the bandwidth absolute frequency response of a multi-layer graphene nanoribbon (MLGNR) multi-walled carbon nanotube (MWCNT) at local, semi-global global interconnect lengths. The transfer function driver-interconnect-load system is obtained by representing line with an equivalent single conductor model either MLGNR or MWCNT. Using response, it observed that higher almost ten times four in comparison to MWCNT for local lengths, respectively.
In the first four decades of semiconductor industry, system performance was entirely dependent on transistor delay and power dissipation. With technology scaling, dissipation significantly reduced; however, a negative impact interconnect realized. The reduction in cross-sectional area copper (Cu) interconnects resulted higher resistivity under effects enhanced grain surface scattering. Moreover, with smaller dimensions operating frequency, Cu is gradually being limited by electromigration...
This research letter presents an accurate and efficient model for rough-edged multi-layered graphene nanoribbon (MLGNR) multi-walled carbon nanotube (MWCNT) bundled interconnects. To address the impact of delay area, analytical finite-difference time-domain real-time simulation based approach are considered. In order to obtain propagation delay, equivalent single conductor (ESC) is accurately presented by simplifying a multi-conductor transmission line (MTL) MWCNT MLGNR The proposed ESC in...
An accurate modelling hierarchy for mixed carbon nanotube (CNT) bundle interconnects is presented. Based on hierarchical modelling, different bundled structures are proposed arrangements of single-walled CNTs (SWCNTs) and multi-walled (MWCNTs). equivalent model CNT bundles has been developed by combination an single conductor (ESC) SWCNTs MWCNTs. Propagation delay under the effect dynamic crosstalk compared these bundles. It observed that crosstalk-induced time improves significantly...
A 3D IC is a chip having multiple tiers of stacked dies. The vertically dies are electrically connected through 3D/vertical interconnects or popularly known as through-silicon-vias (TSVs). Development reliable integrated system largely dependent on the choice filler material used in TSV. Although, several researchers and fabrication houses have demonstrated usage copper material, but, over time it would suffer due to rapid increase resistivity under combined effects enhanced grain boundary...
An integrated circuit (IC), or chip, is a set of electronic circuits and components placed on tiny planar silicon (Si) semiconductor substrate. These electronics are electrically connected to one another with the help vertical conductor elements known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">interconnects</i> . This article presents detailed overview evolution interconnects, highlighting technological milestones that have been...
Emerging nanoelectronic semiconductor devices have been quite promising in enhancing hardware-oriented security and trust. However, implementing hardware primitives methodologies requires large area overhead power consumption. Furthermore, emerging new attack models vulnerabilities are regularly evolving cannot be adequately addressed by current CMOS technology. This paper for the first time presents a comprehensive review of numerous post-CMOS technologies based methodologies, particularly...
In the recent past, various fabrication-related defects such as electromigration-induced open/short faults, interfacial cracks, and thermal stress-induced leakage problems in through silicon via (TSV) have a major impact on reliability performance of TSV-based 3-D integrated circuit (IC). Considering these facts, this article for first time provides equivalent resistance-inductance-conductance-capacitance (RLGC) modeling analysis air gap-defected TSVs comparison with defect free vertical...
In this paper, a more realistic analytical model for randomly distributed mixed carbon nanotube (CNT) bundle (MCB) is presented the analysis of crosstalk induced delay. Several researchers have proposed models interconnects based on single-walled CNT (SWCNT), multi-walled (MWCNT) and most interestingly, spatially arranged CNTs. Although, bundled SWCNTs MWCNTs are easily realizable, but, practically it almost impossible to fabricate MCB with precise arrangements MWCNTs. Motivated by these...
This paper deals with an analysis of propagation delay in carbon nanotube (CNT) bundled interconnects under process-induced variations. An accurate and compact analytical model mixed CNT bundle (MCB) is employed that takes into account the random distribution CNTs having different diameters. Depending on configurations, a multi-conductor transmission line (MTL) presented for MCB, SWCNT, MWCNT interconnects. The performance bundles investigated variations temperature, metallic ratio, contact...
The adoption of a feasible bump shape exerts significant impact on the functionality 3D IC. cylindrical structure, considered among most prevalent shape, endures delay, power loss and crosstalk challenges. tapered based TSV-bump structure recently acquired prominence due to their ultra-low fraction volume coupling, resulting in alleviation delay issues. electrical RLGC modeling has been accomplished for cylindrical, barrel, hourglass structures along with passivation fringing redistribution...
The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, square. At 32[Formula: see text]nm technology, CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via represented an...