<?Pub Dtl=""?> A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed fabricated to demonstrate its zero standby power high performance. The supply voltages of 32 cells along word line (WL) are controlled simultaneously by (PL) driver eliminate the without impact on access time. This fine-grained gating scheme also optimizes trade-off between macro size operation power. butterfly curve for measured be...

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated 90nm CMOS MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power eliminate standby chip. The experimentally shown retain data static noise margin (SNM) 0.32V under V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> =1V. chip 2.19μm <sup...

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, considerably influence the operation margin and power dissipation. It also accelerate speed, which makes possible to simulate three times or more large-scale than when a...

A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F/sup 2/ (F = 0.18 /spl mu/m) on SOI. The named the floating body transistor (FBC) ability to achieve 4F/sup using self-aligned contact technologies and is proved be scalable with respect signal. basic operation was verified by device simulation hardware measurement. An array driving method disclosed which makes selective write possible. signal sensing system consisting pair reference cells written opposite data...

The restructuring of today's computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one the most promising ways to making computers much more efficient with less power. To this end, several possibilities using NV memories logic spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels new discussed. A NV-SRAM cell consisting four transistors two MTJs (4T-2MTJ) shown be candidate for future NV-cache memories. For NV-main memories, we...

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case NFET driver cell, free layers are connected to transistors' sources drains make read-disturb free. The power totally eliminated as line shut down during data hold. noise margin calculated based on experimental MTJ switching enhanced from resistive load SRAM due MTJ's operation. size estimated become smaller than...

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield 68% has been obtained. Device simulation proves that cell is scalable 32nm node keeping signal margin (threshold voltage difference) data retention time constant

The incubation (transit) time of the perpendicular magnetic tunnel junction (MTJ) is found shorter (longer) than in-plane MTJ. By making use time, a new concept proposed for MTJ/CMOS hybrid circuits that operate as fast CMOS without operation power overhead and with negligible MTJ switching error. A nonvolatile latch based on fabricated in 90nm technology to demonstrate 600MHz stable operation.

We propose a novel power-gated microprocessor unit (MPU) using nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By the NV-F/F to store MPU's internal state, this MPU realizes power-gating operation small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than conventional deep power down mode. To achieve short delay, an appropriate circuit, can perform stable high speed store/recall operations, has been developed. The will...

The converter described is a feedback-type voltage regulator which supplies reduced to an entire RAM circuit. A novel timing activation method was introduced save power. has been implemented on experimental 4-Mb dynamic RAM. It found that even faster access time and higher reliability compared conventional design could be achieved by using on-chip shorter channel transistors. This suitable for high-density, high-speed, high-reliability DRAMs with submicrometer

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have newly implemented, namely: 1) optimized well structure and 2) Cu wiring. The design both array device peripheral circuit in order to realize full functionality good retention characteristics. wiring used bit line source line, which increases signal of worst also realizes compatibility standard CMOS process. Scalability FBC down...

The memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.175 /spl mu/m array for first time. is a one-transistor gain cell, which suitable structure future embedded DRAM on SOI wafer. layout and process integration designed from viewpoint logic compatibility without sacrificing data retention characteristics. salicide with poly-Si plug implemented into integration. most important device realizing threshold voltage difference (/spl Delta/ Vth)...

THIS PAPER W-ILL DISCUSS the design of a 49Ib CMOS DRAM that has been fabricated to examine feasibility trench cells, new process and circuit technologies, investigate reliability problem% such as hot carrier effects α-particle induced soft errors. The critical problems for future DRAMS some possible solutions will be reviewed.

A novel FBC with 25nm-thick BOX (buried oxide) structure has been developed. feature of new is scalability in the case thinner SOI, which promises embedded DRAM on SOI future generations. Using 96Kbit array, pause time distribution demonstrated for first time. Due to simplified structure, variation significantly suppressed compared conventional FBC.

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 mu/m/SUP 2/ yielding chip size 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit implemented as mask option to investigate possible solution the MOSFET reliability problem...

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case NFET driver cell, free layers are connected to transistors' sources drains make read-disturb free. The power totally eliminated as line shut down during data hold. noise margin calculated based on experimental MTJ switching enhanced from resistive load SRAM due MTJ's operation. size estimated become smaller than...

A 4-Mb CMOS DRAM measuring 6.9/spl times/16.11 mm/SUP 2/ has been fabricated using a 0.9-/spl mu/m twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5/spl times/5.5 /spl mu/m/SUP each, are incorporated in p-well. novel built-in selftest (BIST) function which enables simultaneous and automatic test of all the memory devices on board is introduced to reduce RAM testing time system. This effective for system maintenance daily start-up even...

A multiple-level 2-bit/cell storage technique for DRAMs (dynamic random-access memories) has been developed. The total RAM area is reduced and the cell array cut in half. Since memory especially defect-sensitive, this highly effective process yield improvement. Reasonable access time realized with technique: 170 ns still fast enough many ASIC (application-specific integrated circuit) applications. This meets requirement of high density moderate speed. It was found that suitable macrocell or...

A one-transistor memory cell on silicon-on-insulator, called floating-body (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state "1"-state, which is a key parameter for realizing large-scale by FBCs, measured analyzed using 96 kb array diagnostic monitor (ADM). function test of ADM yielded fail-bit probability 0.002%. new metric relating to probability, that is, ratio threshold over total variation, introduced applied measurement results. Read current...

Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide and operation, high-density embedded memory achievable.

The robustness of data load metal–oxide–semiconductor/magnetic tunnel junction (MOS/MTJ) hybrid latches at power-on is examined by using Monte Carlo simulation with the variations in magnetoresistances for MTJs and threshold voltages MOSFETs involved 90 nm technology node. Three differential pair type spin-transfer-torque-magnetic random access memory cells (4T2MTJ, 6T2MTJ, 8T2MTJ) are compared their successful power-on. It found that 4T2MTJ cell has largest pass area shmoo plot TMR ratio...

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep data state from being degraded by word-line (WL) disturb due to charge pumping and reduce refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) replenishes "1" cells' bodies with holes which are lost in read write cycle. The power reduced operating S/As asymmetrically between selected unselected thanks that number of be replenished two order magnitude smaller than required writing...

Methods to generate an accurate reference current by averaging multi-pair dummy cells' currents for distinguishing the data in sense amplifiers (S/As) of a large scale memory with resistance change cell is presented and analyzed. The predicted characteristics are confirmed comparing them measurement results functionalities retention time distributions floating body random access (FBRAM). methods found be especially effective situations where signals seriously degraded such as sensing tail...