Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated full adder based on architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium (MgO) barrier MTJs used take advantage of their high magneto-resistance (TMR) ratio spin-injection write capability. The MOS...

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) memory and NAND structure EEPROM discussed. Disturbs during programming, write/erase endurance, charge loss devices reviewed, tunnel oxide interpoly dielectric described. It is shown that bipolarity F-N programming/erase, which used in EEPROM, improves to breakdown decreases stress-induced leakage current.< <ETX...

This paper reviews emerging nonvolatile random access memories (RAM) in recent years. It first benchmarks ferroelectric RAM (FeRAM), phase change (PCRAM), resistive (ReRAM), and spin-torque-transfer magnetic (STT-MRAM), discussing each RAM's features its applications. Then current status of spintronics developments including not only STT-MRAM but also logic LSI is described, which are particularly suitable for working memory

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs embedded that can be used in conventional VLSI circuits systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages devices, especially magnetic tunnel junction (MTJ) circuits, are discussed, current...

Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, example, need a microcontroller unit (MCU) that the ability to process signals and compress data immediately. A previously reported 130nm CMOS FeRAM-based MCU features zero-standby power fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was sufficiently meet application requirements,...

<?Pub Dtl=""?> A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed fabricated to demonstrate its zero standby power high performance. The supply voltages of 32 cells along word line (WL) are controlled simultaneously by (PL) driver eliminate the without impact on access time. This fine-grained gating scheme also optimizes trade-off between macro size operation power. butterfly curve for measured be...

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free high-density fully parallel nonvolatile TCAM. By optimally merging storage function comparison logic into TCAM with logic-in-memory structure, the transistor counts required in become minimized. As result, size becomes 3.14um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> under 90-nm CMOS 100-nm MTJ technologies, which...

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This more tolerant to threshold voltage fluctuation than conventional MCML and suitable gigahertz deep-submicron Using this logic, 8:1 multiplexer (MUX) 1:8 demultiplexer (DEMUX) ICs optical-fiber-link systems have been fabricated with 0.18-/spl mu/m The are faster MUX DEMUX their power consumption less 1/4 that 10-Gb/s made using Si bipolar or GaAs

A compact ternary content-addressable memory (TCAM) cell of 3.15 µm2 with a 0.14 µm complementary metal oxide semiconductor process is realized by the use nonvolatile magnetic tunnel junction (MTJ) devices spin-injection write. This TCAM based on logic-in-memory architecture MTJs needs no standby power, yet allows instant shut-down supply voltage without data backup to an external device.

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronic is capable of fast-read/write with high endurance together back-end-of-the-line (BEOL) compatibility, offering possibility constructing not only stand-alone RAMs and embedded that can be used in conventional VLSI circuits systems but also low-power high-performance CMOS logic employing logic-in-memory architecture. The advantages MTJs are discussed the current status MTJ technology presented along its prospect remaining challenges.

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming serious power-consumption problem that rapidly become dominant constraint on performance improvement today's VLSI processors. Normally-off and instant-on capabilities with small area penalty due to non-volatility three-dimensional-stackability MTJ in above structure allow us apply power-gating technique fine...

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated 90nm CMOS MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power eliminate standby chip. The experimentally shown retain data static noise margin (SNM) 0.32V under V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> =1V. chip 2.19μm <sup...

A magnetic tunnel junction (MTJ)-based logic-in-memory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted dissipation. The proposed nonvolatile designed by establishing an automated design environment MTJ-based logic-circuit IPs and peripheral assistant tools, as well precise MTJ device model produced the test chips. Through measurement...

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, considerably influence the operation margin and power dissipation. It also accelerate speed, which makes possible to simulate three times or more large-scale than when a...

Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive applications, owing to their low-voltage high-speed operation capability in addition high-endurance feature. There three types of spintronics devices with different writing schemes: spin-transfer torque (STT), spin-orbit (SOT), electric field (E-field) effect on magnetic anisotropy. The memories using STT have...

Novel damage control integration process technology has been developed through development of new low-damage MgO deposition process, RIE and low temperature SiN-cap process. Application the to MTJ fabrication enabled us demonstrate an improvement TMR ratio, thermal stability factor, switching efficiency. Moreover, it is shown that endurance fabricated MTJs over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , although factor...

The demand for energy-efficient, high-performance microcontroller units (MCUs) the use in power-supply-critical Internet-of-Things (IoT) sensor-node applications has witnessed a substantial increase. In response, research concerning development of several low-power-consuming MCUs been actively pursued. performance level such MCUs, however, not sufficient, thereby rendering them non-feasible IoT that process large number received signals immediately followed by extraction valuable information...

Abstract Spin‐current generation via the anisotropic spin‐split effect has been predicted in antiferromagnetic RuO 2 , where symmetry of plays a critical role spin–orbit torque (SOT). This phenomenon garnered attention for its potential to enable energy‐efficient spintronic devices, such as SOT magnetic random‐access memory. In this study, high‐quality (100) epitaxial film with well‐controlled triple‐domain‐structure is analyzed, and it confirmed that out‐of‐plane spin‐current independent...

Synthetic antiferromagnetic (AF) pinned layers are widely used in order to reduce the stray field of layer and stabilize magnetic alignment reference perpendicular tunnel junctions (MTJs). Here, a detailed study Re concentration dependence magnitude interlayer exchange coupling (|Jex|) synthetic AF system with an Ir–Re is conducted. We observed strong caused by small amounts addition phase shift peak thinner region systems interlayer. A has anisotropy which stable up 673K annealing,...

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel logic circuits based on architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ spin-injection write capability only one device that has all following superior features as large resistance ratio, virtually unlimited...

By conducting a 1200°C vacuum annealing of 3C-SiC(111) ultrathin film preformed on Si(110) surface, we have succeeded in forming graphene layer Si substrate. Raman-scattering spectrum from this surface presents distinct 2D band, whose deconvolution into four subcomponents indicates that the mostly consists two-layer graphene. The peak position is blue-shifted free-standing formed by mechanical exfoliation method, suggesting compressive stress film. [DOI: 10.1380/ejssnt.2009.107]

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel logic circuits based on architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ spin-injection write capability only one device that has all following superior features as large resistance ratio, virtually unlimited...

A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ make it possible not only to reduce the effect resistance variation, but also enhance programmability values, which achieves sufficient sensing margin even when process variation serious in recent nanometer-scaled VLSI....

In last decade, since high performance MTJ using CoFeB/MgO-based interfacial perpendicular magnetic anisotropy (IPMA) is utilized, STT-MRAM technology has rapidly progressed and mass-production of already started in the semiconductor companies. However, for further expansion MRAM applications markets, higher reliability, larger capacity or speed are required. this invited paper, we describe our recent progresses STT-/SOT-MRAM fabricated under developed 300mm integration process (PVD, RIE...

The development of new functional memories using emerging nonvolatile devices has been widely investigated. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) become technology platform to overcome the issue in power consumption logic for application from IoT AI; however, STT-MRAM a tradeoff relationship between endurance, retention, and time. This is because MTJ device used two-terminal device, excessive read current high-speed readout can cause unexpected data writing,...