A5007702824- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- Parallel Computing and Optimization Techniques
- Advanced Memory and Neural Computing
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- VLSI and FPGA Design Techniques
- CCD and CMOS Imaging Sensors
- Advancements in PLL and VCO Technologies
- Quantum Computing Algorithms and Architecture
- Radiation Effects in Electronics
- Ferroelectric and Negative Capacitance Devices
- Scientific Computing and Data Management
- Advanced Sensor and Energy Harvesting Materials
- Manufacturing Process and Optimization
- Energy Harvesting in Wireless Networks
- Advanced Manufacturing and Logistics Optimization
- Advanced Image Processing Techniques
- Advanced Vision and Imaging
- Advanced Data Storage Technologies
- Radio Frequency Integrated Circuit Design
- Quantum-Dot Cellular Automata
- Security and Verification in Computing
University of Michigan
2015-2024
Google (United States)
2023
Michigan United
2019
Aix-Marseille Université
2014-2015
STMicroelectronics (France)
2014-2015
Institut des Matériaux, de Microélectronique et des Nanosciences de Provence
2014
We describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize goal "democratization hardware design", by reducing cost, expertise, schedule and risk barriers that confront system designers today. The development open-source, self-driving design tools is in itself a "moon shot" with numerous technical cultural challenges. flow incorporates compatible set span logic synthesis, floorplanning, placement, clock tree global routing...
This paper presents a 4+2T SRAM for embedded searching and in-memory-computing applications. The proposed cell uses the n-well as write wordline to perform operations eliminate access transistors, achieving 15% area saving compared with conventional 8T SRAM. decoupled differential read paths significantly improve noise margin, therefore reliable multi-word activation can be enabled in-memory Boolean logic functions. Reconfigurable sense amplifiers are employed realize fast normal or...
This paper presents iRazor, a lightweight error detection and correction approach, to suppress the cycle time margin that is traditionally added very large scale integration systems tolerate process, voltage, temperature variations. iRazor based on novel current-based detector, which embedded in flip-flops potentially critical paths. The proposed flip-flop requires only three additional transistors, yielding 4.3% area penalty over standard D flip-flop. scheme implemented an ARM Cortex-R4...
A 4+2T SRAM is proposed that offers searching and logic functions. The cell uses the N-well as write wordline (WL) eliminates access transistors. Decoupled read paths enable reliable multi-word activation for in-memory Boolean can reconfigure to BCAM/TCAM operations, with 0.13fJ/search/bit at 0.35V. Forty test chips in 55nm deeply depleted channel (DDC) technology achieve worst-case 0.3 V VDDmin.
It is well known that technology scaling has led to increasing process/voltage/temperature/aging margins substantially degrade performance and power in modern processors SoCs. One approach address these large timing the use of specialized registers on critical paths perform error detection correction (EDAC) [1-5]. While promising, previously proposed implementations have been limited several ways. Most notably, they often incur overheads beyond conventional register designs (e.g., 8-to-44...
Energy-optimal operation is one of the key requirements Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination dynamic voltage scaling (DVS) and adaptive body biasing (ABB), energy-optimal achieved with given fixed operating frequency determined by application demands. Based on observation that ratio leakage power can be an accurate indicator for optimal point, proposed method dynamically tracks minimum energy points adjusting supply bias very...
A 32b SoC is designed in 28nm FDSOI to operate either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) 0.33V, with process-temperature compensation. At near threshold, it overcomes low transistor current negative temperatures, the need for extra digital supply IO, and clocking power costs faced by internet-of-things (IoT) wearable systems. The system includes: 1) all-digital single-supply open-loop clock multiplier achieving 1.51 pJ/cycle; 2) a 0.33V/0.45V dual-mode...
An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage conventional implementations replaces flip-flops data key storage with latches using re-timing, saving 25% area 69% power. Along a 2-stage Sbox native GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> ) xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>...
This paper demonstrates a complete wireless sensor node for accurate cellular temperature measurement that includes fully programmable Cortex-M0+ processor, custom SRAM, optical energy harvesting, 2-way communication, and subthreshold sensor. The resolution is 0.034°C RMS, the transmit distance extends to 15.6cm. 0.04mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> (~500× smaller than grain of rice) assembled sensing system (CTS) 24×...
This letter presents an open-source framework for autonomous generation of tapeout-ready temperature sensors. uses a leakage-based digital sensor design as the template. A cell-based methodology is employed to allow full synthesizability and compatibility with computer-aided designs (CADs) flow advanced technology nodes. Furthermore, generator automates end-to-end in Python supports designing completely CAD tools. Verified 64 instances SkyWater 130 nm, also enables low-effort silicon-proven...
We present the world's first autonomous mixed-signal SoC framework, driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process-agnostic framework takes high-level intent as inputs to generate optimized and fully verified blocks using cell-based design methodology. Our approach is highly scalable silicon-proven an prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, temperature sensors integrated processor in 65nm CMOS process. physical all...
SRAM is a key building block in systems-on-chip and usually limits their voltage scalability, due to the major impact of process/voltage/temperature (PVT) variations at low voltages [1]. Assist techniques extend operating range improve bit cell read/write stability [1-5], but cannot mitigate internal sensing delay that needed develop targeted bitline (BL) voltage. Hence, large guard bands performance margins are still ensure correct operation. These increase as supply lowered (Fig. 17.3.1)...
In an initiative to advance the open-source electronic design automation (EDA) and hardware community, Google has been spearheading a global collaborative effort involving investigators from academia, start-ups as well foundries. Open-source silicon being end goal, multiple blossoming projects are supported drive renewed wave break down barriers of EDA tooling ultimately design. This push toward democratization also aims develop release platform silicon-proven analog digital IP blocks serve...
This work presents an open-source methodology to automate the design and layout of a low dropout (LDO) regulator from high-level performance specifications. LDO designs with this have been demonstrated in commercial 65nm, 12nm, 130nm processes Skywater PDK. The tool currently supports 50mV/100mV for input voltage range 0.6V-1.3V (130nm 65nm), 0.6V-0.9V (12nm), 1.8V-3.3V (Skywater 130nm) maximum load current ranging 0.5mA-25mA 1mA-20mA 0.5mA-50mA 130nm). Cell-based approach is adopted using...
Quantum circuit simulation is a challenging computational problem crucial for quantum computing research and development.The predominant approaches in this area center on tensor networks, prized their better concurrency less computation than methods using full vectors matrices.However, even with the advantages, array-based tensors can have significant redundancy.We present novel open-source framework that harnesses decision diagrams to eliminate overheads achieve speedups over prior...
Wireless sensors for IoT applications have become a prominent computing class and are typically severely power constrained. devices deployed in wide range of environments low consumption must be guaranteed across temperature range. The combination dynamic voltage scaling (DVS) adaptive body biasing (ABB) can achieve minimum total energy per cycle, where leakage at an optimal trade-off point [1]. However, due to the dependence on workload fluctuations over time, this operating requires...
This paper presents a single-chip, high-performance, and energy-efficient stereo vision depth-estimation processor for micro aerial vehicles (MAVs). The proposed implements the state-of-the-art semi-global matching (SGM) algorithm to deliver full high-definition (HD, 1920 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\times }$ </tex-math></inline-formula> 1080) stereo-depth outputs with maximum of 38...
Accurate, compact thermal sensors are desirable in many applications, including on-chip temperature monitoring for processors with dynamic throttling and reliability management. Modern limited either area, robustness, or accuracy. This work sidesteps strong linearity requirements reference PTAT elements the sensor by performing a higher-order fitting of more relaxed CTAT using an embedded calculation compute engine. A 24 × 10μm sensing element (40nm CMOS) achieves inaccuracy <;1°C across 30...
This paper presents a PLL-assisted crystal oscillator using current switching phase detector (PD) with intrinsic 90° offset for IoT applications. The PLL provides accurate pulse injection timing into the XO, sustaining its oscillation at only 100mV amplitude and ensuring robustness operation across PVT. technique achieves high energy efficiency avoids use of power hungry amplifiers. Measured is 1.7nW room temperature demonstrated from -20-80°C 3 corner wafers.
This letter presents a fully integrated recursive successive-approximation switched capacitor (RSC) DC–DC converter implemented using an automatic cell-based layout generation in 12-nm FinFET technology. A novel design methodology is demonstrated based on the theoretical analyses of optimal energy operation switched-capacitor (SC) and directly finds parameters from given input specifications. The maintains >75% efficiency across vast range output currents temperatures. Our targets voltage...
Today's open-source chip development ecosystem relies on various Electronic Design Automation (EDA) tools, accessible through permissive licenses GitHub [1] – [3]. As the design matures, EDA tool maintainers gradually incorporate customized features to boost user's experience. Such is case of OpenFASoC, an Open-Source, Fully Autonomous SoC Synthesis that uses customizable Cell-Based Synthesizable Analog Circuits. This process-agnostic delivers, different alternatives, a framework integrated...
A key challenge in the design of on-chip wake-up timers for compact wireless sensor nodes is to achieve high timing accuracy over temperature and supply voltage variation within an ultra-low power budget. We propose a gate-leakage-based frequency-locked timer with first- second-order cancellation achieving 260 ppm/°C from -5 95°C. The consumes 224 pW at 90 Hz output frequency 0.93%/V dependence 1.1-3.3 V range.
The democratization of chip design is revolutionizing the field analog and mixed-signal by incorporating software practices into development process. This has enabled automation tools for improving time to market relieving amount engineering resources required design: often long pole in any tapeout. OpenFASOC, an open-source framework, emerged as a suite that automates By leveraging combination methodologies tools, our framework strikes balance between complexity performance. employs...