A5069179438- VLSI and FPGA Design Techniques
- 3D IC and TSV technologies
- Low-power high-performance VLSI design
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Electronic Packaging and Soldering Technologies
- Copper Interconnects and Reliability
- Green IT and Sustainability
- Electromagnetic Compatibility and Noise Suppression
- Advancements in Photolithography Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Ergonomics and Human Factors
- Natural Language Processing Techniques
- Industrial Vision Systems and Defect Detection
- Manufacturing Process and Optimization
- Computer Graphics and Visualization Techniques
- Model-Driven Software Engineering Techniques
- Embedded Systems Design Techniques
- BIM and Construction Integration
- Advanced Battery Technologies Research
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor Lasers and Optical Devices
- Environmental Impact and Sustainability
- Machine Fault Diagnosis Techniques
- Radiation Effects in Electronics
Arizona State University
2023-2025
University of Minnesota
2019-2022
University of Minnesota System
2019-2021
We describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize goal "democratization hardware design", by reducing cost, expertise, schedule and risk barriers that confront system designers today. The development open-source, self-driving design tools is in itself a "moon shot" with numerous technical cultural challenges. flow incorporates compatible set span logic synthesis, floorplanning, placement, clock tree global routing...
Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks map these fast accurate image-to-image sequence-to-sequence translation tasks. The network takes a as input outputs or IR drop map. We propose two networks: (i) ThermEDGe: static dynamic full-chip estimator (ii) IREDGe: predictor on power, distribution, pad distribution patterns. models design-independent...
Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint semiconductor industry. However, this has led to increased embodied emissions, arising from design, manufacturing, packaging. While existing research developed tools analyze for traditional monolithic systems, these do not apply near-mainstream heterogeneous integration (HI) technologies. HI systems offer significant potential sustainable computing by minimizing emissions...
Designing an optimal power delivery network (PDN) is a time-intensive task that involves many iterations. This paper proposes methodology employs library of predesigned, stitchable templates, and uses machine learning (ML) to rapidly build PDN with region-wise uniform pitches based on these templates. Our applicable at both the floorplan placement stages physical implementation. (i) At stage, we synthesize optimized early estimates current congestion, using simple multilayer perceptron...
The evolution of AI algorithms has not only revolutionized many application domains, but also posed tremendous challenges on the hardware platform. Advanced packaging technology today, such as 2.5D and 3D interconnection, provides a promising solution to meet ever-increasing demands bandwidth, data movement, system scale in computing. This work presents HISIM, modeling benchmarking tool for chiplet-based heterogeneous integration. HISIM emphasizes hierarchical interconnection that connects...
Vectored IR drop analysis is a critical step in chip signoff that checks the power integrity of an on-chip delivery network.Due to prohibitive runtimes dynamic analysis, large number test patterns must be whittled down small subset worst-case vectors.Unlike traditional slow heuristic method selects few vectors with incomplete coverage, MAVIREC leverages machine learning techniques-3D convolutions and regression-like layers-for fast recommending larger exercise scenarios.In under 30 minutes,...
Modern transistors such as FinFETs and gate-all-around FETs (GAAFETs) suffer from excessive heat confinement due to their small size three-dimensional geometries, with limited paths the thermal ambient. This results in device self-heating, which can reduce speed, increase leakage, accelerate aging. paper characterizes temperature for both 7nm FinFET 5nm GAAFET sub-structures analyzes its impact on circuit performance (delay power) reliability (bias instability, hot carrier injection,...
Traditional methods that test for electromigration (EM) failure in multisegment interconnects, over the lifespan of an IC, are based on use Blech criterion, followed by Black's equation. Such analyze each segment independently, but well known to be inaccurate due stress buildup multiple segments. This paper introduces new concept boundary reflections flow ascribes a physical (wave-like) interpretation transient behavior finite line. can provide framework deriving analytical expressions EM...
Due to the unavailability of routing information in design stages prior detailed (DR), tasks timing prediction and optimization pose major challenges. Inaccurate wastes effort, hurts circuit performance, may lead failure. This work focuses on after clock tree synthesis placement legalization, which is earliest opportunity time optimize a “complete” netlist. The article first documents that having “oracle knowledge” final post-DR parasitics enables post-global (GR) produce improved outcomes....
Evaluating CAD solutions to physical implementation problems has been extremely challenging due the unavailability of modern benchmarks in public domain. This work aims address this challenge by proposing a process-portable machine learning (ML)-based methodology for synthesizing synthetic power delivery network (PDN) that obfuscate intellectual property information. In particular, proposed approach leverages generative adversarial networks (GAN) and transfer techniques create realistic PDN...
An innovative ML infrastructure named CircuitOps is developed to streamline dataset generation and model inference for various generative AI (GAI)-based circuit optimization tasks. Addressing the challenges of absence a shared Intermediate Representation (IR), steep EDA learning curves, AI-unfriendly data structures, we propose solutions that empower efficient handling. Our contributions encompass following: (1) labeled property graphs (LPGs) as IR flexible netlist representation parallel...
Traditional methodologies for analyzing electromigration (EM) in VLSI circuits first filter immortal wires using Blech's criterion, and then perform detailed EM analysis on the remaining wires. However, criterion was designed two-terminal does not extend to general structures. This paper demonstrates a first-principles-based solution technique determining steady-state stress at all nodes of interconnect structure, develops an immortality test whose complexity is linear number edges...
Power delivery network (PDN) analysis is a critical aspect of the design cycle to ensure power grid meets current demands chip. Static IR drop simulation, performed as part PDN analysis, crucial estimation worstcase voltage (IR) chip which in turn determines frequency and functionality. Algorithmically, static simulation amounts solving large system linear equations with billions variables computationally very expensive significantly runtimes. This contest aims at leveraging machine learning...
Timing prediction and optimization are challenging in design stages prior to detailed routing (DR) due the unavailability of information. Inaccurate timing wastes effort, hurts circuit performance, may lead failure. This work focuses on after clock tree synthesis placement legalization, which is earliest opportunity time optimize a "complete" netlist. The paper first documents that having "oracle knowledge" final post-DR parasitics enables post-global (GR) produce improved outcomes. Machine...
Timing prediction and optimization are challenging in design stages prior to detailed routing (DR) due the unavailability of information. Inaccurate timing wastes effort, hurts circuit performance, may lead failure. This work focuses on after clock tree synthesis placement legalization, which is earliest opportunity time optimize a "complete" netlist. The paper first documents that having "oracle knowledge" final post-DR parasitics enables post-global (GR) produce improved outcomes. Machine...
Power delivery network (PDN) design is a nontrivial, time-intensive, and iterative task. Correct PDN must consider power bumps, currents, blockages, signal congestion distribution patterns. This work proposes machine learning-based methodology that employs set of predefined templates. At the floorplan stage, coarse estimates current, congestion, macro/blockages, C4 bump distributions are used to synthesize grid for early design. placement incrementally refined based on more accurate...
Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due excessive IR drops. This paper integrates IR-drop-aware analysis and ECO optimization using reinforcement learning (RL). The method operates after physical power grid synthesis, rectifies IR-drop-induced degradation through gate sizing. It incorporates the Lagrangian relaxation (LR) technique into a novel RL framework, which trains relational graph convolutional network (R-GCN) agent...
Large language models (LLMs) serve as powerful tools for design, providing capabilities both task automation and design assistance. Recent advancements have shown tremendous potential facilitating LLM integration into the chip process; however, many of these works rely on data that are not publicly available and/or permissively licensed use in training distribution. In this paper, we present a solution aimed at bridging gap by introducing an open-source dataset tailored OpenROAD, widely...
Traditional electronic design automation (EDA) techniques struggle to fulfill the stringent efficiency and quick turnaround demands of complex integrated systems. Machine learning (ML) strategies for EDA ("ML EDA") are pivotal in transforming address these challenges. However, they encounter significant obstacles due inadequate infrastructure, ranging from datasets software interfaces. This paper demonstrates a infrastructure ML built on two key technologies: (i) OpenROAD's Python APIs, (ii)...