A5100369907- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Nanowire Synthesis and Applications
- Silicon Nanostructures and Photoluminescence
- Ferroelectric and Negative Capacitance Devices
- Turbomachinery Performance and Optimization
- Heat Transfer Mechanisms
- Semiconductor materials and interfaces
- Radio Frequency Integrated Circuit Design
- Refrigeration and Air Conditioning Technologies
- Advanced Memory and Neural Computing
- MXene and MAX Phase Materials
- Phytochemistry and Biological Activities
- Ultra-Wideband Communications Technology
- Electrostatics and Colloid Interactions
- Electrodeposition and Electroless Coatings
- Industrial Technology and Control Systems
- Advancements in Photolithography Techniques
- Laser Design and Applications
- Gyrotron and Vacuum Electronics Research
- Aerosol Filtration and Electrostatic Precipitation
- Supramolecular Self-Assembly in Materials
- Electrokinetic Soil Remediation Techniques
- Electric Power Systems and Control
- VLSI and FPGA Design Techniques
University of Chinese Academy of Sciences
2008-2024
Institute of Microelectronics
2019-2023
Chinese Academy of Sciences
2008-2023
Technical Institute of Physics and Chemistry
2012
Changchun University of Science and Technology
2010
Peking University
2007-2009
Lanzhou Institute of Chemical Physics
2008
In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and impact process variation are investigated for first time. Analog/RF figures merit SNWTs studied, including transconductance efficiency g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , intrinsic gain /g cutoff frequency f xmlns:xlink="http://www.w3.org/1999/xlink">t </sub> maximum oscillation...
Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which a promising candidate beyond fin field effective (FinFETs) technologies in near future. These deal with several challenges brought by shrinking of device dimensions. The preparation inner spacers is one most critical processes GAA nano-scale transistors. This study focuses on two key processes: spacer film conformal deposition and accurate etching. results show that low pressure...
A novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) with self-aligned and replaced high-κ metal gates (HKMGs) is presented for the first time, aiming at a 3 nm technology node beyond. The nVSAFETs were fabricated by an integration flow of Si/SiGe epitaxy, quasi-atomic layer etching (qALE) SiGe selective to Si, formation SiGe/Si core/shell NS/NW structure, building nitride dummy gate, replacement gate. This fabrication method...
A physics-based equivalent-circuit model for on-chip symmetric transformers is presented with all the elements driven from fabrication specifications. Two extra coupled transformer loops are used each coil to parameters of skin effect, proximity and reflective effect substrate eddy current, respectively. Model accuracy under free space first demonstrated using an electromagnetic field solver without considering loss. Several sets were fabricated on a standard 0.18- mum 1P8M RF CMOS...
Ferroelectric vertical gate-all-around field-effect-transistor (Fe-VGAAFET) suits a memory cell with 5 nm technology node and beyond since it is less constrained by gate length, thereby providing sufficient space for the ferroelectric film compared FinFET (Fe-FinFET) lateral field-effect-transistors (Fe-LGAAFET). Also, Fe-VGAAFET achieves multilayer stacking, which further increases integrated density of devices. Here, we develop sandwich (Fe-VSAFETs) large windows (the maximum 2.3 V), high...
The lateral and vertical gate-all-around (GAA) field-effect transistors are considered the most promising candidates for next generation logic device at beyond 3-nm technology node. SiGe plays an important role in these devices as sacrificial layer or channel material needs isotropic etching. In this paper, advanced etching process termed quasi atomic (qALE) is developed with advantages of controllable etch rate atomically smooth surfaces. qALE based on wet chemical etching, which H2O2...
A digital etching method was proposed to achieve excellent control of depth. The characteristics p+-Si and Si0.7Ge0.3 using a combination HNO3 oxidation buffered oxide removal processes were investigated. Experimental results showed that saturates as time goes on because low activation energy its diffusion-limited characteristic. An model developed describe the wet process with nitric acid. calibrated experimental data, saturation time, final thickness, selectivity between obtained. In...
A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of selective to both GeSi and the (111) plane, top-drain implantation, ozone postoxidation (OPO) channel passivation. pVSAFETs, which have hourglass-shaped...
In this study, negative DIBL (NDIBL) due to capacitance is used improve MOSFETs and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) circuits by employing custom-built Simulation Program with Integrated Circuit Emphasis (SPICE) model. A multi-threshold technique was proposed using NDIBL effect, it can be manufactured simple manufacturing process without increasing footprint of transistor. The influence the effect a field-effect-transistor (NCFET) on transistor effective drive...
The morphological evolution of PANI helixes was achieved without the use chiral dopants, but by a facile process through generation onion-like multi-lamellar vesicles used as novel soft-template and liquid crystal acting promoter for polymerization self-assembly, which is breakthrough synthesis helical structures.
Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process challenges of manufacturing vertical SiGe/Si nanowire array by using conventional lithography novel dry atomic layer etching technology. The final results demonstrate that with a diameter less than 20 nm can be obtained. is adjustable an accuracy error 0.3 nm. This technology provides new way for advanced 3D
In this letter, a post-CMOS selectively grown porous silicon (SGPS) technique is proposed to improve the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -factor of integrated inductor. The inductors are fabricated in standard RF CMOS process, and layers after processing from backside wafer. For 2.1-nH inductor 1 poly 3 metal 0.35- 105% increase (from 9.5 19.4) peak achieved. Furthermore, 2.45-GHz voltage-controlled oscillator using SGPS...
Silicon oxynitride (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> N xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> ) is a common barrier material in thin-film encapsulation (TFE) organic light-emitting diode (OLED). Substrate defects, voids and film internal defects occur during SiO deposition process result poor conformity failure. In this work, mathematical model built to evaluate experimental rate high accuracy two...
Vertical-nanowire-FETs (VNW-FETs) get a lot of attentions as promising devices in sub-5 nm nodes. Moreover negative capacitance (NC) is an emerging technique that can break through the lower limit sub-threshold swings (SS) to reduce power consumption MOSFETs. However, suffering from limitation short gate length there lack controllable and integrative structures for high performance VNW-FETs with NC (NC VNW-FETs). In this study, useful structure proposed VNW-FET, which be used density ICs,...
In this letter, post-CMOS substrate selective-transformation engineering based on the selectively grown porous silicon (SGPS) technique is demonstrated to effectively suppress crosstalk. The testing structures for crosstalk isolation are fabricated in a standard 0.18-mum CMOS process, and trenches after processing from backside of wafer. For structure with 250-mum separation Si, 42.8-dB improvement (from -23.5 -66.3 dB) achieved at 2 GHz. characteristics SGPS have been extracted using...
Macroporous silicon arrays (MSA) have attracted much attention for their potential applications in photonic crystals, microchannel plates, MEMS devices and so on. In order to fabricate perfect MSA structure, photo-electrochemical (PEC) etching of the influence current on pore morphology were studied detail. The current-voltage curve a polished n-type wafer was presented aqueous HF using back-side illumination. critical density JPS discussed basic condition steady growth proposed. An indirect...
With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel have emerged excellent choices. The driving forces this choice are full control short effect high carrier mobility in region. In work, a novel process to form structure VGAA transistor Ge is presented. consists multilayers Si0.2Ge0.8/Ge grown on buffer layer by reduced pressure chemical vapor deposition technique. growth...
Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at 3 nm technology node and beyond. Isotropic etching silicon–germanium (SiGe) definition nano-scale channels in vertical GAA tunneling FETs has attracted more attention. In this work, effect doping on digital Si-selective SiGe with alternative nitric acids (HNO3) buffered oxide (BOE) was investigated detail. It found that HNO3 selective to n+-Si, p+-Si,...
For the formation of nano-scale Ge channels in vertical Gate-all-around field-effect transistors (vGAAFETs), selective isotropic etching to Ge0.8Si0.2 was considered. In this work, a dual-selective atomic layer (ALE), including Ge0.8Si0.2-selective and crystal-orientation selectivity oxidation, has been developed control etch rate size nanowires. The ALE p+-Ge0.8Si0.2/Ge stacks with 70% HNO3 as oxidizer deionized (DI) water oxide-removal investigated detail. saturated relative etched amount...
Abstract Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed form vertical transistors. In this work, P-incorporation in etching these MLs followed by selective SiGe lateral direction structures vGAAFET have been studied. Several strategies were proposed epitaxy such hydrogen...
Abstract A new type of vertical nanowire (VNW)/nanosheet (VNS) FETs combining a horizontal channel (HC) with bulk/back-gate electrode configuration, including Bulk-HC and FD-SOI-HC VNWFET, is proposed investigated by TCAD simulation. Comparisons were carried out between conventional VNWFET the devices. exhibits better I on / off ratio DIBL than VNWFET. The impact doping geometric parameters electrical characteristic body factor ( γ ) devices was investigated. Moreover, threshold voltage...
This paper reports a new category of high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> integrated inductor which is realized using post-CMOS selective grown porous silicon (SGPS) technique. The SGPS technique used to effectively reduce low-resistivity substrate loss. Different from other (PS) based techniques, this completely based. inductors are fabricated in standard RF CMOS process firstly and then -factors improved through our...
The defect in multilayer of mask blank can degrade the image quality EUV lithography. It is caused by particles deposited under or inside multilayer, which leads to deformation structure. This impact reflectivity and cause amplitude changes phase shifts, resulting pattern shift critical dimension error lithography imaging. In order improve imaging performance, medium size defects be mitigated shifting techniques, while small only compensated repair meet requirements. Therefore, it necessary...