A5050538615- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Nanowire Synthesis and Applications
- Graphene research and applications
- 2D Materials and Applications
- Quantum and electron transport phenomena
- MXene and MAX Phase Materials
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Topological Materials and Phenomena
- Semiconductor Quantum Structures and Devices
- Photonic and Optical Devices
- Molecular Junctions and Nanostructures
- Plasmonic and Surface Plasmon Research
- Silicon Carbide Semiconductor Technologies
- Thin-Film Transistor Technologies
- Perovskite Materials and Applications
- Surface and Thin Film Phenomena
- GaN-based semiconductor devices and materials
- Carbon Nanotubes in Composites
- Mechanical and Optical Resonators
- Electrostatic Discharge in Electronics
- Advanced Sensor and Energy Harvesting Materials
- Low-power high-performance VLSI design
University of Chinese Academy of Sciences
2016-2025
Institute of Microelectronics
2016-2025
Chinese Academy of Sciences
2016-2025
Zhejiang University
2024-2025
State Key Laboratory of Transducer Technology
2016-2025
Shanghai Institute of Microsystem and Information Technology
2016-2025
Henan University of Technology
2024
State Key Laboratory on Integrated Optoelectronics
2019-2021
National Engineering Research Center of Electromagnetic Radiation Control Materials
2021
University of Electronic Science and Technology of China
2021
We demonstrate theoretically how local strains in graphene can be tailored to generate a valley-polarized current. By suitable engineering of strain profiles, we find that electrons opposite valleys ($K$ or ${K}^{\ensuremath{'}}$) show different Brewster-like angles and Goos-H\"anchen shifts, exhibiting close analogy with light propagating behavior. In strain-induced waveguide, $K$ ${K}^{\ensuremath{'}}$ have group velocities, which used construct valley filter without the need for any...
After more than five decades, Moore’s Law for transistors is approaching the end of international technology roadmap semiconductors (ITRS). The fate complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D in form gate-all-around (GAA) are being considered as an excellent solution to scaling down beyond 5 nm node, which solves difficulties carrier transport channel region mainly rooted short effects (SCEs). parallel Moore, during last two...
We describe a spin logic device with controllable magnetization switching of perpendicularly magnetized ferromagnet / heavy metal structures on ferroelectric (1-x)[Pb(Mg1/3Nb2/3)O3]-x[PbTiO3] (PMN-PT) substrate using current-induced spin-orbit torque. The devices were operated without an external magnetic field and controlled by voltages as low 10 V applied across the PMN-PT substrate, which is much lower compared to previous reports (500 V). deterministic smaller voltage was realized from...
Advancements in the semiconductor industry introduce novel channel materials, device structures, and integration methods, leading to intricate physics challenges when characterizing devices at circuit level. Nevertheless, accurate models for emerging are crucial physics-driven TCAD-to-SPICE flows enable increasingly vital design technology co-optimization (DTCO). Particularly ultra-scaled where quantum effects become significant, this led introduction of empirical model parameters a...
In this work, the contact length scaling in dual-gate (DG) InGaZnO (IGZO) thin film transistors (TFTs) was experimentally investigated. With source/drain metal of Nickel (Ni) deposited ultra-high vacuum condition ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim \,\,{8}\times {10} ^{-{8}}$ </tex-math></inline-formula> Torr), resistance notation="LaTeX">${R}_{C}{)}$ is achieved to be as low...
High-performance negative capacitance p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr O xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) layer are fabricated based on conventional high-κ metal gate fabrication flow. The devices show improved subthreshold swing values [34.5 mV/dec for 500-nm length (L...
A new type of vertical nanowire (NW)/ nanosheet (NS) field-effect transistors (FETs), termed sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that compatible with processes used the mainstream industry proposed for VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were to fabricate pVSAFETs first time. Vertical GAA self-aligned high-k metal gates a small effective-gate-length variation obtained....
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk substrate are systemically investigated. The release process NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio GeSi layer achieved for GeSi/Si stacks samples with different thickness (5 nm, 10 and 20 nm) or annealing temperatures (≤900 °C). Furthermore, influence ground-plane (GP) doping in sub-fin region...
In recent years, wearable sensors have revolutionized health monitoring by enabling continuous, real-time tracking of human and performance. These noninvasive devices are usually designed to monitor physical state biochemical markers. However, enhancing their functionalities often demands intricate customization designers additional expenses for users. Here, we present a strategy using assembled modular circuits customize wearables. The can be effortlessly reconfigured meet various specific...
The implementation of vertically stacked gate-all-around nanosheet FET (GAA NSFET) may help improve the performance static random access memory (SRAM) for design flexibility with variable NS widths. However, method that often relies on increasing device width higher driving current is to cause an increased SRAM cell area and degrade scalability transistor in advanced nodes. In this article, innovated bitcell hybrid integration Si NSFET Si/SiGe super-lattice FinFET (SL-FinFET) one proposed...
We study electron tunneling through a planar magnetic and electric barrier on the surface of three-dimensional topological insulator. For double structures, we find (i) directional-dependent which is sensitive to field configuration gate voltage, (ii) spin rotation controlled by (iii) many Fabry-P\'erot resonances in transmission determined distance between two barriers, (iv) electrostatic potential can enhance difference magnetization configurations, consequently lead giant...
We present a comprehensive theoretical investigation of the quantum confinement limited mobility in Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -channel gate-all-around nanosheet field effect transistor for 5-nm node. The study encompasses physics-based mechanical models both P and NMOS with specified channel/wafer orientations channel thicknesses: (1) k.p model Poisson...
In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal FinFET flow implemented GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H <sub...
Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM desired to capture nonlinear device electronic characteristics their high-order derivatives. However, for novel devices in advanced future technologies, establishing based on analytical equations extracting parameters becomes tedious. The fitting capability outputs' derivatives also limited. These drawbacks hinder fast accurate evaluation cycles. We develop a multigradient neural...
Doped HfO2 thin films, which exhibit robust ferroelectricity even with aggressive thickness scaling, could potentially enable ultralow-power logic and memory devices. The ferroelectric properties of such materials are strongly intertwined the voltage-cycling-induced electrical structural changes, leading to wake-up fatigue effects. Such field-cycling-dependent behaviors crucial evaluate reliability HfO2-based functional devices; however, its genuine nature remains elusive. Herein, we...
We develop a method to fabricate an undoped Ge quantum well (QW) under 32 nm relaxed Si0.2Ge0.8 shallow barrier. The bottom barrier contains (650 °C) and Si0.1Ge0.9 (800 such that variation of content forms sharp interface can suppress the threading dislocation density (TDD) penetrating into well. SiGe introduces enough in-plane parallel strain (ε∥ -0.41%) in heterostructure field-effect transistors with buried channel obtain ultrahigh two-dimensional hole gas (2DHG) mobility over 2 × 106...
Abstract In this work, a conventional HfO 2 gate dielectric layer is replaced with 3-nm ferroelectric (Fe) HZO in the stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and differential resistance (NDR), are clearly observed for both p- n-type HZO-based FinFETs. These characteristics attributed to enhanced ferroelectricity hafnium zirconium oxide (HZO) film, caused by Al doping from TiAlC capping...
The valley Zeeman splitting of monolayer two-dimensional (2D) materials in the magnetic field plays an important role and spin manipulations. In general, a high (6–65 T) low temperature (2–30 K) were two key measurement conditions to observe resolvable 2D current reported experiments. this study, we experimentally demonstrate effective scheme by employing circular dichroism (MCD) spectroscopy, which enables us distinguish under relatively 1 T at room temperature. MCD peaks related both A B...
In this paper, a near-ideal subthreshold swing MoS2 back-gate transistor with an optimized ultrathin HfO2 dielectric layer is reported detailed physical and electrical characteristics analyses. Ultrathin (10 nm) films created by atomic-layer deposition (ALD) at low temperature rapid-thermal annealing (RTA) different temperatures from 200 °C to 800 have great effect on the characteristics, such as (SS), on-to-off current (I ON/I OFF) ratio, etc, of devices. Physical examinations are...