A5040575776- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Thin-Film Transistor Technologies
- Nanowire Synthesis and Applications
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- MXene and MAX Phase Materials
- Silicon and Solar Cell Technologies
- Silicon Carbide Semiconductor Technologies
- Semiconductor materials and interfaces
- 2D Materials and Applications
- Particle Detector Development and Performance
- Transition Metal Oxide Nanomaterials
- ZnO doping and properties
- Radiation Detection and Scintillator Technologies
- Silicon Nanostructures and Photoluminescence
- Metal and Thin Film Mechanics
- CCD and CMOS Imaging Sensors
- Advanced Surface Polishing Techniques
- Quantum and electron transport phenomena
- Carbon Nanotubes in Composites
- Diamond and Carbon-based Materials Research
- Graphene research and applications
- Ferroelectric and Piezoelectric Materials
University of Chinese Academy of Sciences
2016-2025
Institute of Microelectronics
2016-2025
Chinese Academy of Sciences
2016-2025
Beijing Normal University
2025
State Key Laboratory of Remote Sensing Science
2025
Academia Sinica
2024
North China University of Technology
2020-2024
Guangzhou Institute of Energy Conversion
2023
State Key Laboratory on Integrated Optoelectronics
2013-2019
Institute of Microelectronics
2015
ABSTRACT Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes been added three-dimensional (3D) channels with enhanced control carrier conductance provide higher electrostatic integrity operating currents within same device footprint. Beyond 1-nm node, Moore’s law...
Abstract An effective stacked memory concept utilizing all‐oxide‐based device components for future high‐density nonvolatile structure data storage is developed. GaInZnO (GIZO) thin‐film transistors, grown at room temperature, are integrated with one‐diode (CuO/InZnO)–one‐resistor (NiO) (1D–1R) oxide node elements, fabricated temperature. The low growth temperatures and fabrication methods introduced in this paper allow the demonstration of a stackable array as well characteristics. Benefits...
The diameter of roots is pivotal for studying subsurface root structure geometry. Yet, directly obtaining these parameters challenging due their hidden nature. Ground-penetrating radar (GPR) offers a reproducible, nondestructive method detection, but estimating from B-Scan images remains challenging. To address this, we developed the CycleGAN-guided multi-task neural network (CMT-Net). It comprises two subnetworks, YOLOv4-Hyperbolic Position and Diameter (YOLOv4-HPD) CycleGAN. YOLOv4-HPD...
Amorphous-gallium-indium-zinc-oxide (a-GIZO) thin filmtransistors (TFTs) are fabricated without annealing, using processes and equipment for conventional a-Si:H TFTs. It has been very difficult to obtain sound TFT characteristics, because the a-GIZO active layer becomes conductive after dry etching Mo source/drain electrode depositing a-SiO2 passivation layer. To prevent such damages, N2O plasma is applied back surface of channel before deposition. plasma-treated TFTs exhibit excellent...
We have demonstrated a self-aligned top-gate amorphous gallium indium zinc oxide thin film transistor (a-GIZO TFT). It had field effect mobility of 5 cm2/V s, threshold voltage 0.2 V, and subthreshold swing V/decade. Ar plasma was treated on the source/drain region a-GIZO active layer to reduce series resistance. After treatment, surface divided into In-rich In-deficient regions. The TFT also constant sheet resistance 1 kΩ/◻ for thickness over 40 nm. interface between Mo metal plasma-treated...
In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit a plot reciprocal channel versus gate voltage yields threshold 3.5 V and field-effect mobility about 13.5 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vldrs. Furthermore, in a-GIZO TFTs, most current flows distance range 0-0.5 mum from edge...
High-performance negative capacitance p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr O xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) layer are fabricated based on conventional high-κ metal gate fabrication flow. The devices show improved subthreshold swing values [34.5 mV/dec for 500-nm length (L...
A new type of vertical nanowire (NW)/ nanosheet (NS) field-effect transistors (FETs), termed sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that compatible with processes used the mainstream industry proposed for VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were to fabricate pVSAFETs first time. Vertical GAA self-aligned high-k metal gates a small effective-gate-length variation obtained....
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk substrate are systemically investigated. The release process NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio GeSi layer achieved for GeSi/Si stacks samples with different thickness (5 nm, 10 and 20 nm) or annealing temperatures (≤900 °C). Furthermore, influence ground-plane (GP) doping in sub-fin region...
The implementation of vertically stacked gate-all-around nanosheet FET (GAA NSFET) may help improve the performance static random access memory (SRAM) for design flexibility with variable NS widths. However, method that often relies on increasing device width higher driving current is to cause an increased SRAM cell area and degrade scalability transistor in advanced nodes. In this article, innovated bitcell hybrid integration Si NSFET Si/SiGe super-lattice FinFET (SL-FinFET) one proposed...
A fully transparent nonvolatile memory with the conventional sandwich gate insulator structure was demonstrated. Wide band gap amorphous GaInZnO (a-GIZO) thin films were employed as both charge trap layer and transistor channel layer. An excellent program window of 3.5 V a stressing time 100 ms achieved through well-known Fowler–Nordheim tunneling method. Due to similar energy levels extracted from experimental data, asymmetrical program/erase characteristics are believed be result strong...
Amorphous gallium-indium-zinc-oxide (GIZO) thin film transistors with short channels of 50 nm were successfully fabricated by e-beam lithographic patterning. The GIZO showed a high mobility 8.2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vldrs on-to-off current ratios up to 10 xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . Excellent channel characteristics also obtained small shift the threshold voltages and no degradation...
We present a comprehensive theoretical investigation of the quantum confinement limited mobility in Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -channel gate-all-around nanosheet field effect transistor for 5-nm node. The study encompasses physics-based mechanical models both P and NMOS with specified channel/wafer orientations channel thicknesses: (1) k.p model Poisson...
In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal FinFET flow implemented GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H <sub...
In this paper, an N-type silicon line tunneling TFET (LT-TFET) with ultra-shallow N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> pocket was proposed. The formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy and spike annealing. Due to Ge PAI, probability improved significantly. As a result, high on-state current of 40 μA/μm, minimum subthreshold swing (SS) 69 mV/decade average SS 80 over 5...
Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM desired to capture nonlinear device electronic characteristics their high-order derivatives. However, for novel devices in advanced future technologies, establishing based on analytical equations extracting parameters becomes tedious. The fitting capability outputs' derivatives also limited. These drawbacks hinder fast accurate evaluation cycles. We develop a multigradient neural...
Doped HfO2 thin films, which exhibit robust ferroelectricity even with aggressive thickness scaling, could potentially enable ultralow-power logic and memory devices. The ferroelectric properties of such materials are strongly intertwined the voltage-cycling-induced electrical structural changes, leading to wake-up fatigue effects. Such field-cycling-dependent behaviors crucial evaluate reliability HfO2-based functional devices; however, its genuine nature remains elusive. Herein, we...
Complex nonlinear dependence of ultra-scaled transistor performance on its channel geometry and source/drain (S/D) doping profile bring obstacles in the advanced technology path-finding optimization. A machine learning-based multi-objective optimization (MOO) workflow is proposed to optimize sub-3-nm node gate-all-around (GAA) three-layer-stacked nanosheet transistors (NSFETs) accounting for key knob S/D profile. The artificial neural network (ANN) trained learn compact current–voltage (...
Abstract In this work, a conventional HfO 2 gate dielectric layer is replaced with 3-nm ferroelectric (Fe) HZO in the stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and differential resistance (NDR), are clearly observed for both p- n-type HZO-based FinFETs. These characteristics attributed to enhanced ferroelectricity hafnium zirconium oxide (HZO) film, caused by Al doping from TiAlC capping...
The effects of Ni and Ni0.83Pt0.17 alloy electrodes on the resistance switching dc-sputtered polycrystalline NiO thin films were investigated. initial off-state resistances similar to that Pt∕NiO∕Pt film. However, after first cycle switching, significantly decreased in with electrode. It can be attributed migration from films. improvement data dispersion parameters is explained terms decrease effective thickness resulting Ni.
We fabricated gallium-indium-zinc oxide (GIZO) thin film transistors (TFTs) having a double-gated (DG) structure and studied the back gate effect on device performance. DG GIZO TFTs showed better threshold voltage (Vth), swing factor (S), on/off current than those with single gate. With variation in bias, performance significantly changes due to modification of field distribution near channel. It is believed that our an effective way improve suppress formation accumulation layer at surface.
Currently, both high-density 3-D stacking nonvolatile (NV) memory and embedded NV in advanced systems on panel (SOPs) urgently demand the assistance of new functional transition metal-oxide materials. This is to overcome serious fabrication issues encountered use conventional Si or poly-crystalline materials, as well increase storage density with lower process cost. paper reports fully structure operated by an ionic amorphous oxide semiconductor a wide energy band gap (> 3.0 eV) Ga <sub...