A5038724985- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Nanowire Synthesis and Applications
- MXene and MAX Phase Materials
- 2D Materials and Applications
- Thermal properties of materials
- Advanced Memory and Neural Computing
- Semiconductor materials and interfaces
- Silicon Carbide Semiconductor Technologies
- Thin-Film Transistor Technologies
- Neural Networks and Reservoir Computing
- Radiation Effects in Electronics
- Molecular Junctions and Nanostructures
- Electrostatic Discharge in Electronics
- Quantum-Dot Cellular Automata
- Semiconductor Quantum Structures and Devices
- Integrated Circuits and Semiconductor Failure Analysis
Institute of Microelectronics
2020-2025
Chinese Academy of Sciences
2020-2025
Huawei Technologies (China)
2024-2025
University of Chinese Academy of Sciences
2020-2023
Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM desired to capture nonlinear device electronic characteristics their high-order derivatives. However, for novel devices in advanced future technologies, establishing based on analytical equations extracting parameters becomes tedious. The fitting capability outputs' derivatives also limited. These drawbacks hinder fast accurate evaluation cycles. We develop a multigradient neural...
Complex nonlinear dependence of ultra-scaled transistor performance on its channel geometry and source/drain (S/D) doping profile bring obstacles in the advanced technology path-finding optimization. A machine learning-based multi-objective optimization (MOO) workflow is proposed to optimize sub-3-nm node gate-all-around (GAA) three-layer-stacked nanosheet transistors (NSFETs) accounting for key knob S/D profile. The artificial neural network (ANN) trained learn compact current–voltage (...
Impact ionization effect has been demonstrated in transistors to enable sub-60 mV dec−1 subthreshold swing. However, traditionally, impact silicon devices requires a high operation voltage due limited electrical field near the device drain, contradicting low energy purpose. Here, we report vertical swing composed of graphene/silicon heterojunction drain and channel. This structure creates avalanche phenomenon leads steep switching silicon-based device. Experimental measurements reveal small...
The cold source field-effect transistor (CSFET), enabled by novel engineering, is a promising alternative to achieve sub-60 mV/dec steep-slope switching. For the first time, we develop an industry-standard TCAD approach for CSFET with effective carrier density of states (DOS) model which captures underlying physics DOS injection, and thermalization in device. simulation scheme uses nonequilibrium Green's function (NEGF) calibration. effects rethermalization, channel tunneling are extensively...
This work experimentally demonstrates a novel molybdenum disulfide (MoS 2 ) field‐effect transistor (FET) based on negative capacitance (NC) and Dirac source (DS) hybrid technique. The synergistic mechanism enhances both carrier transport gate control, enabling steep slope significantly increased on‐state current. By this design, NCDS FET achieves ultrahigh current of 100 μA, low average subthreshold swing (SS) 60.3 mV dec −1 over approximately two orders magnitude in I DS minimum 6...
A novel comb-like-channel field-effect transistor (CombFET), which is the combination of fin (FinFET) and nanosheet FET (NshFET) geometries in channel region, proposed evaluated numerically for first time. Our simulations show that: 1) with same footprint, CombFET ON-current 43% higher than FinFET 53% gate-all-around (GAAFET) due to its larger effective width relieved quantum confinement 2) CombFETs have great advantages performance optimization through surface orientation over FinFETs...
Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by series of parasitic parameters these SRAM cells will diminish scaling benefit introduced new transistor architectures. In this article, we propose universal methodology to determine layout optimization direction 6T (6T-SRAM) studying sensitivity 6T-SRAM cell various parameters. And adopt method optimize CFET structure under advanced...
Complementary FET (CFET) is a promising candidate for CMOS scaling beyond 3-nm technology node. In this article, novel hybrid channel CFET (HC-CFET) proposed, which takes advantage of the vertical structure and simultaneously co-optimizes preferred high-electron/hole-mobility surface NMOS/PMOS on one substrate. The flexible combination nanowires (NWs) nanosheets (NSs) in HC-CFET allows NMOS to have (100) orientation, while PMOS has (110) orientation without increasing footprint pillars....
In this article, one feasible fabrication approach for novel fishbone FETs using the channel-first and single work function metal (sWFM) processes is proposed investigated by 3-D technical computer-aided design (TCAD) simulations. Through a small modification on process of general gate-all-around (GAA) nanosheet (NSFETs), special fishbone-like channel composed vertically stacked Si NSs sandwiched SiGe nano-fins experimentally demonstrated process. The simulated electrical characteristics...
—In this paper, the gate/drain voltage-dependent self-heating effect (SHE) in gate-all-around (GAA) nanosheet field transistors (NSFETs) and FinFETs is investigated by 3-D TCAD simulation. The drain current decreases because of SHE dependent on voltage different devices. Furthermore, lattice maximum temperature-rise (ΔTmax), which directly leads to degradation due stronger carrier mobility scattering under higher temperature, exhibits complex trends with increased voltages. ΔTmax increases...
Recently, the cold source field-effect transistor (CSFET) has emerged as a promising solution to overcome Boltzmann tyranny in its ballistic regime, offering steep-slope subthreshold swing (SS) of less than 60 mV/decade. However, challenges arise due scattering, particularly from inelastic which can lead significant degradation SS through carrier thermalization. In this study, we delve into theoretical investigation electronic excitation/relaxation dynamic process using state-of-the-art...
Artificial synapses are key elements in building bioinspired, neuromorphic computing systems. Ferroelectric field‐effect transistors (FeFETs) with excellent controllability and complementary metal oxide semiconductor (CMOS) compatibility favorable to achieving synaptic functions low power consumption high scalability. However, because of the only nonvolatile ferroelectric (Fe) characteristics FeFET, it is difficult develop bioplausible short‐term for spatiotemporal information processing. By...
In this letter, the endurance characteristics of negative capacitance (NC) FinFETs with an ultra-steep subthreshold swing (SS) and negligible hysteresis were investigated by examination approach to emulate long-term logic operation. Detailed variation for different electrical parameters are summarized devices subjected up 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> switching pulse cycles. The average values threshold voltages (V...
Source engineering is an emerging technique to achieve steep-slope switching FET. To bridge the new carrier filtering mechanism and device performance, a multiscale simulation framework presented in this article applied Si nanowire (NW) cold source FET (CSFET). By fit-parameter-free density functional theory (DFT) method, key component of (CS) design for broken-gap-like band alignment high injection demonstrated. The novel also verified entire scale with fully quantum atomistic tight-binding...
In this study, a SPICE model for Negative Capacitance FinFET (NC-FinFET) based on the BSIM-CMG and Landau-Khalatnikov (L-K) equation is developed. The areas of ferroelectric layer (AFE) work functions (WFs) n-NC-FinFET p-NC-FinFET are adjusted to reduce shift threshold voltage. As result, NC-FinFET-based seven-stage ring oscillator (RO) has smaller delay, energy can down 72.2 % compared with FinFET-based RO under same delay. Furthermore, 6T SRAM read write time lower static power than SRAM....
Si-based cold source field-effect transistor (CSFET) combines the benefits of sub-60-mV/dec steep-slope switching, high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> current, and compatibility with current Si CMOS process technology. Therefore, it is a promising candidate for future energy-efficient logic For first time, we present...
In this paper, we demonstrate the prediction of important figures merit (FoMs) including threshold voltage (Vth), subthreshold swing (SS), on-state (Ion) and off-state (Ioft) current, vertically stacked lateral nanosheet field-effect-transistors (NSFET) using 1) an artificial neural network generated by genetic algorithm (GA) 2) a conventional multi-layer (NN). Our work shows that trained GA-based NN has great capability predicting FoMs with average coefficients determination at 0.992, which...
Cold Source Field Effect Transistor (CSFET) enabled by source engineering is a promising candidate to achieve unique sub-60 mV/dec steep-slope switching. For the first time, we present an industry-standard multiscale TCAD framework for CSFET with proposed effective cold carrier distribution model, which captures underlying physics of injection efficiency, and thermalization. The incorporates Non-Equilibrium Green's Function (NEGF) simulations validation. effects geometry configuration are...
Recently, cold source transistor (CSFET) with steep-slope subthreshold swing (SS) < 60 mV/decade has been proposed to overcome Boltzmann tyranny in its ballistic regime. However the scattering, especially by inelastic scattering may lead serious SS degradation through carrier thermalization. In this study, electronic excitation/relaxation dynamic process is investigated theoretically virtue of state-of-the-art nonadiabatic molecular dynamics (NAMD) method, i.e., mixed quantum-classical NAMD....
This article presents a device-circuit co-optimization on Negative Capacitance FinFETs (NC-FinFETs). A physics-based SPICE model that combines industry-standard BSIM-CMG and Landau Khalatnikov (LK) equation is developed for the NC-FinFETs. Different ferroelectric areas (AFE) are selected to analyze characteristics of The influences work function (WF) capacitance matching NC-FinFETs investigated further optimize DC performance inverters. Based model, we simulate transient ring oscillator (RO)...
With novel energy-filtering switching mechanism enabled by broken-gap-like source engineering, steep slope and high on-state current can be obtained in cold FET (CSFET). In order to account for the mechanism, effective carrier distribution model is developed drift-diffusion (DD) method equivalent charge correction term incorporated into industry standard BSIM-CMG model. We present a Si nanowire (NW) CSFET as potential candidate advanced technology node. Steep SS approaching 31/27 mV/dec I...