Wireless power transfer (WPT) technology has drawn much attention due to its advantages such as safety, convenience, and non-contact. For some movable devices intelligent inspection robot, the constant output voltage is very important ensure normal operation. In order improve system efficiency steadiness of voltage, a maximum tracking charging method proposed for dynamic WPT system. this method, mutual inductance optimal input can be estimated accurately no matter coupling coefficient...

A noise-shifting coupling network is proposed for nonlinear passively coupled quadrature voltage-controlled oscillators (QVCOs). Both detailed analysis and circuit implementation demonstrate that the noise contribution by can be minimized re-aligning phases of modulation function impulse sensitivity with a reduced magnitude. In addition, QVCO also incorporates transformer-feedback technique to improve its performance in terms phase noise, error, low supply voltage. Fabricated 65-nm CMOS...

Ring-VCO-based PLLs are popular because of their compact chip area and wide tuning range compared with LC-VCO-based PLLs. However, they typically have higher jitter larger frequency drift due to high sensitivity PVT variations. Several PLL architectures were proposed reject the phase noise reduce [1,2]. an architecture-level limitation, these phase-noise-rejection inevitably degrade settling time. To suppress large (PN) supply sensitivity, a Type-III was provide low-frequency loop gain by...

A high-order cascaded phase-locked loop (PLL) architecture using a sub-sampling delay-locked (DLL) is proposed to break the tradeoff between bandwidth and number of integrator in feedback without significantly degrading settling time or reference spur. clock-skew-sampling phase detector also extend stable detection range detector. Implemented 65-nm CMOS process, prototype two-stage third-order PLL measures 4.2-μs time, 1.05-ps integrated jitter, -113-dBc/Hz in-band noise at 2.1-GHz output...

This paper presents a power efficient static frequency divider (SFD) for wideband operation. Series inductive peaking technique is utilized to construct broadband input network of the divider. The aspects design using are supported with exhaustive simulations. prototyped divided-by-two implemented in 65 nm LP CMOS technology. Measurement results show that core dissipates less than 3.3 mA average current from 1.2 V supply, while operating 1 39 GHz 0 dBm power.

A wireless power transfer (WPT) system can bring convenience to human life, while a leakage magnetic field around the be harmful humans or environment. Due application limitations of aluminum and ferrite materials, it is urgent find new type shielding material. This paper first proposes detailed model analysis method matrix metamaterial (MSM), which applied low-frequency WPT in an electric vehicle (EV). The MSM placed on top side EV shield from all positions. To explore its function,...

This paper presents a noise-shifting coupling network to minimize the phase noise contribution from devices of quadrature voltage-controlled oscillators (QVCOs). Through capacitive feedback, noisy currents are shifted be orthogonal their impulse sensitivity function (ISF). Fabricated in 65nm CMOS technology, 7.9-GHz QVCO prototype measures -143dBc/Hz at 10-MHz frequency offset and minimum IQ error 0.23 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

A low-power phase-tracking receiver (PTRX) is proposed featuring a sub-harmonic mixer with local oscillator (LO) operating at half of the carrier frequency. co-design methodology together current reuse technique adopted to further improve power efficiency. Fabricated in 65nm CMOS process, PTRX prototype measures noise figure 7.1dB and sensitivity -88dBm J-Mb/s BLE Gaussian-Frequency-Shift-Keying (GFSK) data while consuming 750μW 0.4/0.6V supply voltages.

Due to the limitation of rated current and cooling conditions on traditional single inverter inductive power transfer (IPT) system, output primary side cannot meet requirement high-capacity battery supercharge technology. As an effective solution, multi-parallel inverters IPT system can not only improve source but also stability due its fault-tolerance performance. Aiming at low efficiency systems under light load, this paper proposes a dynamic module adjustment scheme for overall in whole...

The paper analyzes the principle of technique using low voltage current source to improve power supply rejection ratio (PSRR) operational amplifiers (OPAs). has advantage decreasing parasitic gain from with no detrimental effect on output swing. A single two-stage Miller compensated OPA is presented as a prototyped circuit. simulation results proposed show that 38 dB and 17 improvement PSRR at DC 10MHz respectively compared without suggested Near rail-to-rail swing 489 MHz bandwidth (GBW)...

Abstract With the fast development of renewable energy, system operators intend to require energy generation have more grid support capabilities. This paper studies grid‐connected control strategy a battery‐free medium‐voltage direct current (MVDC) with distributed photovoltaic units (DPVGUs), aiming realize rapid function AC frequency. Firstly, scheme for MVDC can keep some reserve capacity is provided. At this moment, DPVGUs execute master‐slave coordinated strategy, that is, master DPVGU...

A 60-GHz sub-sampling PLL (SSPLL) employs a differential tuning loop to suppress the reference spur. The VCO frequency is differentially tuned only by NMOS transistors. An injection-locked divider (ILFD) with 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order resonant tank employed between and phase detector (PD) further minimize spur even without an isolation buffer. Fabricated in 65nm CMOS, prototyped SSPLL measures RMS jitter...

The overlapped transmitters IPT system with multi-inverters in parallel can effectively improve the power capacity. Compared single transmitting coil, avoid generation of circulating current. Aiming at imbalanced current due to deviation resonant inductors and delay driving signal. A phase synchronization strategy based on PS-PWM is proposed. In this method, difference currents flows primary coils be reduced. At same time, sharing among different modules realized synchronously. 2 kW...

General methods of SC networks design for bandgap reference are proposed. The based on the conversion between parallel and series connection capacitors. prototyped is designed in 65 nm LP CMOS process. Simulation result shows that temperature coefficient voltage achieved to 25 ppm/°C from −20 100°C .

With the fast development of renewable energy, system operators intend to require energy generation have more grid support capabilities ensure safe operation AC grid. This paper studies grid-connected control strategy a battery-free medium-voltage DC (MVDC) with distributed photovoltaic units (DPVGUs), aiming realize rapid function frequency. Firstly, master-slave coordinated (MSCC) DPVGUs is proposed. Under this strategy, master DPVGU maximum dynamic output characteristics adopts an...