This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including proportional (P-path) and an integral (I-path), with 0.8 V supply voltage. A differential master-slave sampling filter (MSSF), replacing the charge pump (SSCP), composed P-path to avoid degraded feature caused by decreasing of The I-path is built rail-to-rail SSCP suppress phase noise voltage-controlled oscillator (VCO) trouble locking at non-zero offset (as in type-I PLL). proposed design implemented...

The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive system with optimized eye-opening monitor proposed. designed based on the asynchronous statistic eye diagram tracking algorithm, obtained by undersampling low-speed clock. With into loop, combined continuous-time linear (CTLE) completed. And inductor peaking technology used improve capacity compensation. SMIC 28 nm CMOS process...

Meconopsis quintuplinervia is regarded as a valuable medicinal plant in Tibetan system. This species distributed Qinghai, Xizang, Sichuan, Shanxi ,Gansu and Hubei provinces of the People's Republic China. Genetic variation 16 M. populations sampled from Qinghai Gansu China was examined by random amplified polymorphic DNA markers (RAPDs). In total, 225 scored bands were 17 primers used. Of loci, 192(85.33%) polymorphic, total genetic diversity (Ht) 0.2954 Shannon’s information index (I)...

An adaptive continuous-time linear equaliser using the optimised spectrum balancing (SB) method is proposed. The SB extended with a frequency detector to promote compensation ability of an and completes optimal equalisation decision for multi-data rates. active inductor peaking technology adopted increase bandwidth equaliser, save chip area power consumption. Based on Huaili Microelectronics Corporation (HLMC) 40 nm CMOS process achieve overall design, consumption are 32.11 mW at 20 Gbit/s...

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for high-speed serial interface. In the transmitter, complementary MOS H-bridge output driver with common mode feedback (CMFB) circuit was used to achieve stipulated over process, and temperature (PVT) variations. The receiver composed of pre-stage shifter rail-to-rail comparator. an error amplifier shifted input signal required range, thereby following comparator obtained maximum...

A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode (VM) and current (CM) output driver architectures, a low power CM reverse scaling bias filtering technique proposed. 2-tap filter used to reduce intersymbol interference caused by low-pass channel, speed, combined serializer implemented convert 10 bit parallel data into stream. The whole fabricated in 65 nm 1.2 V/2.5 V CMOS technology. It provides...

This work investigated the nonlinear behaviors of disk resonator. Generally, nonlinearity occurs in resonators with small stiffness, such as cantilever, bridge, etc. However, it was observed that radial-contour-mode micromechanical resonator large stiffness and high quality factor (Q) also suffers when a bias voltage is applied. The shows linear response 10 V atmosphere room temperature. vibrates vacuum or at low temperature (below 110 K), even 6 V. effect closely related to change factor,...

This study presents an 8 Gbps low-power source-series terminated (SST) transmitter for high-speed serial links. The proposed consists of a novel hybrid 20:2 multiplexer followed by three-tap feed-forward equalizer (FFE) and shunt path SST driver. In addition, high-precision impedance calibration circuit with slice unit replication is to match the characteristic channel, whose maximum error 0.002%. Fabricated in 55-nm CMOS technology has area 0.024 mm2. Measurement results show that achieves...

Abstract The formation control problem was researched for a fixed-wing unmanned aerial vehicle (UAV) swarm. kinematic model built UAV considering the lumped disturbances. disturbance observers were designed to estimate disturbances in finite time. desired swarm represented by virtual structure. backstepping controller every complete maintaining task. sigmoid tracking differentiator (STD) added controller, order settle of “explosion complexity”. numerical simulation executed show procedure...

A multi-standard compatible clock and data recovery circuit (CDR) with a programmable equalizer wide tracking range is presented. Considering the jitter performance, chip area, CDR employs first-order digital loop filter, two 6-bit DACs high linearity phase interpolators to achieve resolution low area. Meanwhile greater than ±2200 ppm, making this proposed suitable for embedded serial links. test was fabricated in 55 nm CMOS process. The measurements show that can BER < 10−12 meet tolerance...

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of receiver for serial interface, which is compliant with many communication specifications such USB2.0, PCI-E2.0 and Rapid IO. The low high frequency loops are merged to decrease effect delay between two paths, in addition, infinite input impedance facilitates cascade stages order improve boosting gain. implemented circuit architecture could facilitate wide range from 1 3.3 Gbps different...

An adaptive decision feedback equalizer (DFE) with floating tap architecture is proposed. eye height detector designed to perform the number selection of DFE taps. optimized sign-sign least mean square (SSLMS) algorithm developed automatically update coefficients Based on a 55 nm CMOS process, receiver an operation range 2.5 10 Gbps designed. The simulation results show that able provide 8-17 dB compensation ability, and power consumption 10.9 mW at Gbps.

This article presents a low power digital controlled oscillator (DCO) with an ultra duty cycle correction (DCC) scheme. The DCO the complementary cross-coupled topology uses controllable tail resistor to improve current efficiency. A robust scheme is introduced replace self-biased inverters save further. proposed implemented in Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. measured phase noise at room temperature −115 dBc/Hz 1 MHz offset dissipation of 210...

In order to improve the collision avoidance capability of unmanned aerial vehicle (UAV) formation, a new kind UAV formation control algorithm was developed based on combining consensus and artificial potential field (APF). The controller consisted three sub-controllers. first distributed that controlled UAVs maintain desired shape. second an APF avoided collisions among UAVs. third between obstacles in task space. Numerical simulation performed validate effectiveness designed controller....

In order to make a research on the vehicle's ABS and AFS system, fuzzy neural network controller was designed basis of electric steering braking models.Then genetic algorithms used improve parameters membership function.For purpose stability, compensatory .Finally, Matlab/Simulink simulation software has been in analysis.The result proves that no matter how working conditions changes, system still good tracking performance .The systemic robustness is more stronger it also enhances utility...

This paper refers to the HAPC of 400mm single stand reversible cold rolling mill, establishing mathematical model, simplifying and reducing orders for system transfer function on foundation reasonable assumption.This also designs PID LADRC order model uses fuzzy adaptive do online optimization parameters LADRC.In end, shows simulation program controllers mentioned above.The results show that has less overshoot, shorter settling time, better robustness stronger ability restrain...

This paper mainly for the joint control methods of spacecraft return Capsule's temperature and humidity have been studied.According to characteristics humidity, it designs object model decoupling controller on basis model.Using a PID based CMAC neural network Smith Predictor Controller approaches design complex controllers.Using toolbox MATLAB software simulates system, changes interference parameters.The simulation shows that composite has flexibility adaptability network, but also high...

Abstract To tackle the high latency and slow encoding speed of 8B/10B encoder circuits in high-speed serial interfaces, a parallel structure for polarity pre-processing based on logic operations is proposed to optimize performance this article. Firstly, process divided into coding two pipeline stages. This method equals each stage’s delay decreases waiting period. Additionally, employs critical paths multi-stage heterodyne gates series. Therefore, effect number input bytes path can be...

Abstract The reconfiguration problem was researched for the homogenous fixed-wing unmanned aerial vehicle (UAV) swarm. kinematic model of a UAV constructed. virtual structure expressed desired swarm configuration. A node in represented position UAV. improved artificial physics (AP) method used to produce attraction repulsion designed UAVs avoid collisions among them during reconfiguration. controller included attraction, repulsion, and damp term. term reduced chattering process UAV’s flight...

An efficient Physical Coding Sublayer operating at 500MHz has been implemented based on 65 nm CMOS process for PCI Express 2.0, which was integrated into PHY with physical media attachment layer. Two methods of 8b10b codec were compared in area and dynamic power consumption. A reset controller initialization, elastic buffer clock compensation built-in-self-test circuit employed. The synthesized the speed SS an about 5500 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...