A5032768794- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Photonic and Optical Devices
- Optical Network Technologies
- Low-power high-performance VLSI design
- Advanced Wireless Communication Techniques
- CCD and CMOS Imaging Sensors
- Error Correcting Code Techniques
- Advanced Memory and Neural Computing
- Microwave Engineering and Waveguides
- Semiconductor Lasers and Optical Devices
- Full-Duplex Wireless Communications
- Terahertz technology and applications
- Power Line Communications and Noise
- Superconducting and THz Device Technology
- Coding theory and cryptography
- VLSI and Analog Circuit Testing
- Phase-change materials and chalcogenides
- Advanced Power Amplifier Design
- Neural Networks and Reservoir Computing
- Semiconductor materials and devices
- Ferroelectric and Negative Capacitance Devices
- Millimeter-Wave Propagation and Modeling
IBM Research - Zurich
2014-2025
IBM (United States)
2013-2015
ETH Zurich
2007
Graz University of Technology
2007
Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s Ethernet require ADCs with more than 50GS/s at least 5 ENOB to enable complex equalization in the digital domain. SAR interleaved made impressive progress recent years. First CMOS 6b conversion rates exceeding 20GS/s were presented, proving that are an optimal choice for high-speed moderate resolution. We present ADC architecture based on asynchronous redundant core element. It was measured up a sampling rate of...
We present a 256×256 in-memory compute (IMC) core designed and fabricated in 14nm CMOS with backend-integrated multi-level phase-change memory (PCM). It comprises 256 linearized current controlled oscillator (CCO)-based ADCs at compact 4µm pitch local digital processing unit performing affine scaling ReLU operations A novel frequency-linearization technique for CCOs is introduced, leading to accurate on-chip matrix-vector-multiply (MVM) when operating over 1 GHz. Measured classification...
High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</sub> , comparator noise limits the SNDR ADCs, gain stages necessary higher - either as pre-amplifiers or between pipelined stages....
Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking, redundant capacitive DACs (CDAC), multi-bit decisions per step and interleaved have been presented. We present an asynchronous single-channel achieving 1.2GS/s 1V supply by using two comparators alternation to relax comparator reset timing. The achieves 39.3dB SNDR 34fJ/conversion-step...
The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards the 100Gb/s+ regime [1]. Although these are still definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In foreseeable future, a high-performance TX consist CMOS DSP frontend followed by high sampling rate converter [2,3], whose design remains significant challenge. This paper presents 112Gb/s SST Tx that...
This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates fully digital equalization data-path, with synthesized and automatically placed routed signal processor (DSP) following 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). prototype chip implemented in 14-nm FinFET process demonstrates lane data rate of 56 Gb/s...
Digital-to-analog converter (DAC)-based transmitters are suited to support different modulation formats (e.g., NRZ, PAM-4, OFDM), long-channel equalization (incl. roaming taps) or even amplitude reduction for reflection mitigation at short channels. Compared with a conventional FFE, less complex and more uniform high-speed analog frontend can be designed in DAC TX if the number of taps is large >5) because performed digital signal processing (DSP) unit running sub-rate. However, this imposes...
Upcoming standards such as OIF CEI-25LR and CEI-28SR demand transmitter circuits above 20Gb/s [1]-[3] with stringent jitter requirements. The SST driver topology, which has been previously demonstrated at lower data rates [4], is an attractive solution it enables multiple termination options low power consumption. In addition, its single-ended topology facilitates architecture in the delay mismatch between true complementary output can be adjusted, desirable for transmission over long...
Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require ADCs with more than 50GS/s at least 5 ENOB to enable complex digital equalization, a growing number of appropriate designs have been presented [1-4], mostly time-interleaved SAR ADCs. Most these were not intended for input frequencies up Nyquist report an range approximately 20GHz, often equivalent the analog 3dB bandwidth. Ultimately, bandwidth is less relevant SNDR high because FIR filter can...
This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that scheme, which combines analog filters and decision-feedback compensation on the receiver (RX) side only, can efficiently remove patterns in straight channels as well boards with reflections due to via stubs. An eight-lane RX has been manufactured 32-nm SOI CMOS validate our findings. A CTLE eight-tap decision feedback equalizer equalize channel...
This paper describes the implementation of a 4-level pulse-amplitude-modulation (4-PAM) receiver consisting 6-bit time-interleaved successive-approximation analog-to-digital converter (TI-SAR ADC), followed by fully digital speculative 2-tap decision-feedback equalizer (DFE) operating at one-fourth modulation rate. The receiver, implemented in an experimental chip fabricated 32 nm SOI CMOS, is designed to recover data 56Gb/s over channel with attenuation 11 dB 14 GHz. power consumption 202.7...
This brief presents an RFSoC-based functional verification platform for a 2-lane pulse amplitude modulation (PAM) transceiver (TRX) datapath supporting 4-level PAM (PAM-4) and 8-level (PAM-8). Digital-to-analog converters (DACs) analog-to-digital (ADCs) existing on the ZU28DR RFSoC are used as digital front-ends of transmitter (TX) receiver (RX), respectively. All equalization circuits adaptation engines required modern >112 Gb/s DAC/ADC-DSP-based TRX (excluding clock recovery) implemented...
The limited supply voltage of today's state-of-the-art CMOS technologies makes the design high-speed transmitters at signaling swings above typical 1 V a challenging task. Higher-voltage TX amplitude is not only required in older I/O standards and legacy applications, but also emerging electro-optical extensions where high swing combined with operation desired. Higher helps meet certain applications losses introduced by high-density package constraints can be compensat ed to some extent....
The increasing bandwidth demand in data-centers requires wireline transceivers supporting >50Gb/s/lane data-rates with low power consumption. Because link utilization is <;10% for 99% of the links [1] a promising way to reduce consumption fine-grained gating, where powered off during idle time. For rapid on/off functionality be efficient short data bursts, needs wake up within few ns, which challenging at high speeds. Burst mode operation was previously demonstrated 25Gb/s 18.5ns lock-time...
An asynchronous 48× interleaved SAR ADC optimized for high SNDR above 20 GHz input frequency operating at 20-40 GS/s is presented. The features an 8-channel interleaver with clock demultiplexing enhanced bandwidth, a power- and area-optimized 2-stage ADC, bandwidth adjustment in the sampling path. At 32 199 mW power consumption it achieves 47.3 dB near DC 37.8 40 core chip area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>...
The increasing demand on bandwidth for communicating among processors through wired interconnects in large-scale servers motivates the increase lane-data-rate from current 28Gb/s to 56Gb/s or further. Recently published works [1-3] demonstrated ADC-based receiver (RX) prototypes equalizing >56Gb/s PAM-4 symbols legacy channels with pre-FEC BERs of less than 2E4 satisfying IEEE p802.bj/bs BER requirements. While RXs provide strong equalization performance using a large number feed-forward...
An area- and power-optimized asynchronous 32× interleaved SAR ADC achieving 36 GS/s at 110mW with 1V supply on the interleaver 0.9 V ADCs is presented. The features a 2-channel data demultiplexing for enhanced bandwidth, power- area-optimized binary ADC, an clocked reference buffer tunable constant-current source. It achieves 32.6dB SNDR up to 3GHz 31.6dB 18GHz input frequency 98fJ/conversion-step core chip area of 340×140μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB and 78.7dB SFDR with 0.8V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</inf> , xmlns:xlink="http://www.w3.org/1999/xlink">diff</inf> input amplitude at Nyquist. The key elements are a comparator inverter-based preamplifier SAR-based common-mode regulation. regulation adjusts the common mode on sample-by-sample basis to improve rejection. consumes 7.0mW from...
The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. power consumption the VD 105mW at supply voltage 0.7 V, corresponding to an energy efficiency 4.1 pJ/b. A data rate 30.4 Gb/s achieved with 5.3 pJ/b 0.8 V. VD, implemented in experimental chip fabricated 14-nm CMOS FINFET, exploits set-partitioning principles and embedded per-survivor decision feedback reduce complexity consumption. active area 12...
The implementation of a 64x time-interleaved ADC in 32nm CMOS SOI is analyzed. Measurement results confirm 33 dB SNDR up to 19.9 GHz at 90 GS/s and 1.2V supply. Architecture details analysis show insights into limitations potentials the chosen architecture. In par-ticular input bandwidth concern for ADCs more than 64 GS/s, as larger number sampling switches in-creases parasitic load reduces bandwidth. Insights on simplified interleaver structures existing solutions issues are highlighted...