A5014994900- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Photonic and Optical Devices
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Semiconductor materials and devices
- Semiconductor Lasers and Optical Devices
- Advanced Memory and Neural Computing
- Optical Network Technologies
- Ferroelectric and Negative Capacitance Devices
- CCD and CMOS Imaging Sensors
- Advanced Wireless Communication Techniques
- Advanced DC-DC Converters
- Advanced Optical Sensing Technologies
- Wireless Power Transfer Systems
- Error Correcting Code Techniques
- VLSI and Analog Circuit Testing
- 3D IC and TSV technologies
- Machine Learning in Materials Science
- Semiconductor Quantum Structures and Devices
- Quantum and electron transport phenomena
- Phase-change materials and chalcogenides
- Electromagnetic Compatibility and Noise Suppression
- Silicon Carbide Semiconductor Technologies
IBM Research - Zurich
2016-2025
IBM (United States)
2011-2015
ETH Zurich
2004
Board of the Swiss Federal Institutes of Technology
2004
Politecnico di Milano
1993-1994
An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation achieved by converting each sample with two alternate comparators clocked asynchronously redundant capacitive DAC constant common mode to improve the accuracy comparator. A low-power, reference buffer used, fractional voltages are provided reduce number unit capacitors (CDAC). The stacks...
We present a 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at compact 4- notation="LaTeX">$\mu \text{m}$ pitch local digital processing...
Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s Ethernet require ADCs with more than 50GS/s at least 5 ENOB to enable complex equalization in the digital domain. SAR interleaved made impressive progress recent years. First CMOS 6b conversion rates exceeding 20GS/s were presented, proving that are an optimal choice for high-speed moderate resolution. We present ADC architecture based on asynchronous redundant core element. It was measured up a sampling rate of...
We present a 256×256 in-memory compute (IMC) core designed and fabricated in 14nm CMOS with backend-integrated multi-level phase-change memory (PCM). It comprises 256 linearized current controlled oscillator (CCO)-based ADCs at compact 4µm pitch local digital processing unit performing affine scaling ReLU operations A novel frequency-linearization technique for CCOs is introduced, leading to accurate on-chip matrix-vector-multiply (MVM) when operating over 1 GHz. Measured classification...
For an on-chip or fully integrated microprocessor power-delivery system, the power converter must 1) be designed using same technology as microprocessor, 2) deliver high density to supply a core with small area overhead, 3) achieve efficiency, and 4) perform fast regulation over wide voltage range for dynamic frequency scaling (DVFS). On-chip switched-capacitor (SC) converters have gained increasing popularity this application due their ease of integration only transistors capacitors readily...
High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</sub> , comparator noise limits the SNDR ADCs, gain stages necessary higher - either as pre-amplifiers or between pipelined stages....
Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking, redundant capacitive DACs (CDAC), multi-bit decisions per step and interleaved have been presented. We present an asynchronous single-channel achieving 1.2GS/s 1V supply by using two comparators alternation to relax comparator reset timing. The achieves 39.3dB SNDR 34fJ/conversion-step...
A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features look-ahead speculation relax DFE timing 4 unitinterval. analog front end includes transadmittance inductorless variable amplifier, resulting low power...
A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) 100 Gb/s communication systems. The suitable ADCs where the analog input bandwidth concern and enables a tradeoff between different architectures respect to bandwidth, hold time sampled signal, constraints on clock path. at 6 8 b resolution implement inline demux 32χ 64χ interleaving achieve 36 GS/s 110 mW 90 667 mW, respectively. both exceeds...
The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards the 100Gb/s+ regime [1]. Although these are still definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In foreseeable future, a high-performance TX consist CMOS DSP frontend followed by high sampling rate converter [2,3], whose design remains significant challenge. This paper presents 112Gb/s SST Tx that...
A 24-72-GS/s 8-b time-interleaved analog-to-digital converter (ADC) is presented which exceeds 39-dB SNDR at low input frequency and 30-dB Nyquist. High Nyquist achieved by 16 parallel sampling switches driven short clock pulses. Clock-pulse edges can be shifted digitally to reduce the impact of timing mismatch. total 64 asynchronous successive approximation (SAR) ADCs supply voltage convert sampled voltages. The SAR use a differential capacitive DAC, one comparator per decision, include...
The growing demand for higher data rates in wireline communications has led to emerging standards the 100Gb/s+ range using PAM-4 signaling. ADC-based receivers have demonstrated robust operation over channels with high losses (>20dB) [1], but their power consumption (>500mW/lane excluding DSP) is prohibitive applications requiring large port counts short-reach chip-to-chip and chip-to-module links (such as OIF-CEI-112G-VSR/XSR/USR). This work demonstrates a dual PAM-4/NRZ RX implemented 14nm...
An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages. In this unified architecture parallel coarse channel has been eliminated recursively using previous stage as for each following stage. This new a 10-bit ADC six folding-by-3 stages with total order 729. At 1.0 GS/s, interleave-by-2 achieves <±0.2 LSB DNL, ¿ ±0.5...
The future trends in microprocessor supply current requirements represent a bottleneck for next generation high-performance microprocessors since the number of pins will constitute an increasingly larger fraction total package available. This leaves few available signaling. On-chip power conversion is means to overcome this limitation by increasing input voltage - thereby reducing and performing final on chip itself. paper details design implementation on-chip switched capacitor converters...
A low-power receiver circuit in 32 nm SOI CMOS is presented, which intended to be used a source-synchronous link configuration. The design of the was optimized for power owing assumption that protocol enables periodic calibration during does not have deliver valid data. In addition, it shown transceiver and effect high-frequency transmit jitter can reduced by implementing linear equalizer only on receive side avoiding feed-forward (TX-FFE). On level, uses switched-capacitor (SC) approach...
Granular power delivery with per-core regulation for microprocessor has the potential to significantly improve energy efficiency of future data centers. On-chip switched capacitor converters can enable such granular given a high efficiency, density, fast response time, and output converter design. This paper details implementation an on-chip voltage regulator in 32 nm SOI CMOS technology deep trench capacitors. A novel feedforward control reconfigurable is presented. The reduces droop...
On-chip (or fully integrated) switched-capacitor (SC) voltage regulators (SCVR) have recently received a lot of attention due to their ease monolithic integration. The use deep trench capacitors can lead SCVR implementations that simultaneously achieve high efficiency, power density, and fast response time. For the application granular distribution many-core microprocessor systems, on-chip must maintain an output above certain minimum level U <sub...
Germanium avalanche photodiodes (APD's) working biased above the breakdown voltage detect single optical photons in near-infrared wavelength range. We give guidelines for selection of devices suitable photon-counting applications among commercial samples, and we discuss detail how should be operated to achieve best performance, both terms noise-equivalent power (NEP) timing-equivalent bandwidth. introduce driving electronics show that, measurements fast signals, adoption single-photon...
The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in technologies. Existing modeling frameworks do not a comprehensive manner take effect on converter into account. This paper extends an existing SC state space framework to include capacitor. developed model is used Pareto optimization procedure optimally select component values 2:1 converter. Implemented 32 nm SOI CMOS technology that features...
Performing computations on conventional von Neumann computing systems results in a significant amount of data being moved back and forth between the physically separated memory processing units. This costs time energy, constitutes an inherent performance bottleneck. In-memory is novel non-von approach, where certain computational tasks are performed itself. enabled by physical attributes state dynamics devices, particular, resistance-based nonvolatile technology. Several such as logical...
This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates fully digital equalization data-path, with synthesized and automatically placed routed signal processor (DSP) following 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). prototype chip implemented in 14-nm FinFET process demonstrates lane data rate of 56 Gb/s...
Digital-to-analog converter (DAC)-based transmitters are suited to support different modulation formats (e.g., NRZ, PAM-4, OFDM), long-channel equalization (incl. roaming taps) or even amplitude reduction for reflection mitigation at short channels. Compared with a conventional FFE, less complex and more uniform high-speed analog frontend can be designed in DAC TX if the number of taps is large >5) because performed digital signal processing (DSP) unit running sub-rate. However, this imposes...