A5101620711- Video Coding and Compression Technologies
- Advanced Data Compression Techniques
- Digital Filter Design and Implementation
- Biometric Identification and Security
- Advanced Optical Imaging Technologies
- Embedded Systems Design Techniques
- Advanced Vision and Imaging
- Music and Audio Processing
- Image and Video Quality Assessment
- Consumer Perception and Purchasing Behavior
- Speech and Audio Processing
- Speech Recognition and Synthesis
- User Authentication and Security Systems
- Interconnection Networks and Systems
- graph theory and CDMA systems
- Photorefractive and Nonlinear Optics
- Computer Graphics and Visualization Techniques
- Digital Holography and Microscopy
- Advancements in PLL and VCO Technologies
- Embedded Systems and FPGA Design
- Numerical Methods and Algorithms
- Neural Networks and Applications
- Engineering Applied Research
- Multimedia Communication and Technology
- Advanced Image and Video Retrieval Techniques
University of Seoul
2004-2022
Samsung (South Korea)
2013-2021
Korea Institute for Curriculum and Evaluation
2018
National Police Hospital
2017
Sejong University
2009-2011
Chosun University
2006
University of Southern California
2005
Engineering Systems (United States)
2005
Korea Institute of Science & Technology Information
2002
Korea Advanced Institute of Science and Technology
1994-2002
Abstract Since its discovery almost 70 years ago, the hologram has been considered to reproduce most realistic three dimensional images without visual side effects. Holographic video extensively researched for commercialization, since Benton et al. at MIT Media Lab developed first holographic systems in 1990. However, commercially available displays have not introduced yet several reasons: narrow viewing angle, bulky optics and heavy computing power. Here we present an interactive slim-panel...
In this paper, we present the world's first single-chip field-programmable gate array holographic video processor. It makes 16 computer-generated color holograms of resolution 1920 × 1080 in a second. uses an off-the-shelf commercial liquid crystral display for spatial light modulator. To build processor, used layer-based hologram (CGH) algorithm and hardware efficient CGH architecture using fixed-point arithmetic. The processor provides moving with low cost, small footprint, high energy...
Under background noise environments, the performance of Query-by-Singing/Humming (QbSH) system is considerably degraded. Since human pitch information used as a feature vector for QbSH system, robust estimation algorithm inevitable. Thus, novel pitch-estimation method proposed by integrating temporal-autocorrelation and spectral-salience methods. As pre-processing block, spectral smoothing applied to enhance stationarity noisy input signal. To calculate similarity between MIDI database...
In the midst of background noise environments, performance speaker recognition (SR) systems is considerably degraded. To estimate model mismatch between training and evaluation data, we also propose an intra Kullback-Leibler distance (intra-KLD) measure. Based on intra-KLD, SR using speech enhancement (SE) multi-condition (MC) can be predicted with reduced computational complexity. Since SE cannot fully remove real-world without modifying clean signal, trained only a signal represent data...
The architecture and the implementation of a 2K/4K/8K-point complex fast Fourier transform (FFT) processor for an OFDM system are presented. can perform 8K-point FFT every 273 /spl mu/s, 2K-point 68.26 mu/s at 30 MHz which is enough symbol rate. based on Cooley-Tukey (1965) algorithm decomposing long DFT into short length multi-dimensional DFTs. transposition shuffle memories used transforms. CORDIC employed twiddle factor multiplications in each dimension. A new generation method also...
A simple two-step search (2SS) algorithm for motion estimation and its FPGA implementation are proposed in this paper. The has an excellent trade-off between performance hardware cost. Simulation results show that the of is very close to classical full (FS) algorithm. a low computational complexity. By using only two processing elements, architecture cost, memory bandwidth requirements, high speed. With resource may be used mobile real-time video applications. We have prototyped it as IP...
A new nonlinear skewing scheme is proposed for parallel array access. We introduce a Latin square(perfect square) which has several properties useful sufficient condition the existence of perfect squares and simple construction method are presented. The resulting provides conflict free access to various subsets an N x using memory modules. When number modules even power two, address generation performed in constant time circuit. This first that achieves rows, columns, diagonals, N/ sup 1/2/...
To heighten the biometrics security level, feature extraction and verification need to be performed within smart cards, not in external card readers. However, chip has very limited processing capability, typical fingerprint algorithms may executed on a state-of-the-art card. Therefore, this paper presents system-on-chip (SoC) implementation of algorithm which can integrated into cards. implement ridge-following onto resource-constrained SoCs, been modified increase efficiency hardware. Each...
This study analyzed previous research on competency-based curriculum in Korea over approximately the last 10 years and derived implications for future research. Most importantly, to analyze meaning characteristics of competence, studies must clarify concrete components structures competence rather than provide a simple theoretical explanation. Fourth, defined key subject relationship between two, but these terms is still unclear. In particular, cultivation competencies education Therefore,...
Using biometrics to authenticate a person's identity has several advantages over the present practices of Personal Identification Numbers or passwords. To gain maximum security in authentication system using biometrics, computation as well store biometric template take place smart card. However, it is challenging integrate into card because limited resources such processing power and memory space. In this paper, we propose an area-time-accuracy efficient hardware design for fingerprint...
In this paper, we propose a multi-function unit which can support DMX512, UART, IrDA, PWM, timer, counter, and protocol bridges in single hardware IP. Embedded systems are required to various peripheral functions according their applications. Efficient supports for essential. The efficiently integrates the above by exploiting similarities signal formats structures of peripherals. be effectively used LED lighting Firstly, it protocols popular such as DMX512 PWM. Secondly, configured operate...
This research proposes new system which finds the music by using Query-by-humming (QBH). For finding a stored music, features of humming data are selected G.729 feature extractor. We normalize extracted mean-shifting, median filtering, average filtering and min-max scaling methods. Then corresponding is matched based on dynamic time warping (DTW) algorithm. As experiment, we compared matching performance database Roger Jang's Corpus in MIREX.
This paper proposes a Fractional Motion Estimation(FME) unit for H.264/AVC video codec standard. The proposed FME uses full-search algorithm. consists of interpolation unit, comparator metadata processing Current Block(CB) buffer, and Reference Block(RB) SRAM address generator. processes 30 QCIF frames in second at 150MHz. is part Estimation(ME) unit. ME 2 stage pipeline. One Integer Estimation(IME) the other IME share RB SRAM. It takes about 3000∼9000 cycles to process one MacroBlock(MB)...
This paper presents a fast mode decision algorithm and its hardware structure for H.264/AVC intra prediction. For 4×4 luma blocks, the uses only 8 prediction samples to reduce number of possible modes from 9 4. The are easier generate than original used in Values close values samples. 16×16 chroma directions each it reduces 4 2. Overall, 17 8. Experimental results show that has less degradation peak signal-to-noise ratio those existing algorithms. computation time by performing blocks parallel.
This paper presents a unified transform unit that can efficiently perform forward integer transform, quantization, dequantization, inverse and Hadamard in H.264/AVC. To reduce hardware cost, the proposed architecture uses shifters, adder/subtractors instead of multipliers for quantization de-quantization, reuses 1-D all supporting transforms. Hardware utilization is maximized to achieve required performance with low cost. It takes about 250 cycles macroblock, additional 35 The process 6,000...
본 논문에서는 LED 조명 통신을 위한 재구성형 주변장치유닛을 제안한다. 조명시스템을 임베디드 장치에서는 다양한 통신 프로토콜이 요구된다. 이러한 프로토콜로는 UART, SPI, IrDA 등의 직렬 통신, DALI나 DMX512와 같은 조명제어 통신이 있다. 프로토콜 요구사항을 각 IP로 개별 구현하여 만족시킬 경우 비용 및 전력 효율이 떨어질 수 프로토콜의 신호 형식을 분석하여 IrDA, DALI, DMX512의 기능을 통합하는 방법을 제안한 주변장치유닛은 구현 방법에 비해 57% 감소된 양의 게이트수를 사용한다. 또한 네트워크를 유연하게 구현하기 위해 사용될 있는 매핑테이블 기반의 DALI-ZigBee 인터페이싱 이 사용하면 DALI와 ZigBee를 혼용한 구성의 네트워크 시스템을 효율적으로 구현할 조명시스템 플랫폼을 구성하여 유무선 네트워크의 동작을 검증하였다. 논문에서 주변장치유닛과 방법은 구현하는 데에 In this paper, a reconfigurable...
This paper presents a pulse width modulation (PWM) inverter intellectual property (IP) for high-fidelity audio applications. PWM inverters are more power efficient than analog amplifiers and can be designed in smaller size amplifiers. A high performance consists of several modules including oversampler, cross point deriver, noise shaper generator. These usually implemented by software on digital signal processors. shows how to design these hardware. An architecture was with VHDL. The used as...
정보기술의 디자인 트렌드는 시대에 따라 빠르게 변해왔으며, 최근의 정보 디스플레이의 베젤리스 디스플레이가 대세이다. 또는 에지리스 디스플레이는 휴대폰 새로운 트렌드로 부 상하고 있다. 본 논문에서는 이른바 디스플레이라고 불리는 기기 면적 대비 높은 화면 비율을 갖는 터치 패널 조립 공정에 적합한 차광 테이프를 개발하였다. 테이프는 자외선 경화형 아크릴계 감압성 점착제를 PET 필름 위에 롤투롤 공정으로 코팅하여 제조하였다. 점착제는 톨루엔을 전혀 사 용하지 않는 친환경적인 제조 방법으로 합성되었다. 제조된 테이프의 점착력은 자동화된 인장시험기로 분석하 였으며, 형상유지 특성인 칙소성은 주사 전자 현미경으로 분석하였다. 그 결과 터치패널 디스 플레이의 점착력과 우수한 칙소성을 나타내었다. 이러한 기능성 개발은 동안 칙소성 부족으로 인하여 야기되었던 디스플레이 공정의 생산성향상 및 품질 안정성 향상에 기여할 것으로 기대된다.