Jannick Kjær Jørgensen

ORCID: 0000-0003-4151-2494
Publications
Citations
Views
---
Saved
---
About
Contact & Profiles
Research Areas
  • Silicon Carbide Semiconductor Technologies
  • Electromagnetic Compatibility and Noise Suppression
  • Advanced DC-DC Converters
  • Multilevel Inverters and Converters
  • Electrostatic Discharge in Electronics
  • Copper Interconnects and Reliability
  • Advancements in Semiconductor Devices and Circuit Design
  • Electronic Packaging and Soldering Technologies
  • Power Line Inspection Robots
  • Induction Heating and Inverter Technology

Aalborg University
2019-2024

Semikron (Germany)
2024

Danfoss (Germany)
2024

Increased switching speeds of wide bandgap (WBG) semiconductors result in a significant magnitude the displacement currents through power module parasitic capacitances that are inherent packaging design. This is increasing concern, particularly case newly emerging medium-voltage (MV) SiC MOSFETs since can be several order higher due to fast transients and increased voltage magnitudes compared their Si counter parts. The severity intensifies when current becomes comparable fraction rated...

10.1109/jestpe.2019.2939644 article EN IEEE Journal of Emerging and Selected Topics in Power Electronics 2019-09-05

Recent developments within the field of medium voltage wide-bandgap semiconductor devices are drawing attention from both researchers and industries due to demanding requirements for more efficient high-power energy conversion. The rapid development has entailed an increased awareness negative impact rate change in voltage, d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> /d xmlns:xlink="http://www.w3.org/1999/xlink">t</i> , its...

10.1109/tpel.2023.3269582 article EN IEEE Transactions on Power Electronics 2023-04-24

This article proposes a general physics-based model for identifying the parasitic capacitance in medium-voltage (MV) filter inductors, which can provide analytical calculations without using empirical equations and is not restricted by geometrical structures of inductors. The elementary capacitances MV inductor are identified, then equivalent between two terminals derived under different voltage potential on core. Further, three-terminal circuit, instead conventional two-terminal proposed...

10.1109/tpel.2020.3003157 article EN publisher-specific-oa IEEE Transactions on Power Electronics 2020-06-17

This paper presents a 10 kV SiC MOSFET based power stack, featuring medium voltage conversion with simple two-level source converter topology. The design of the (MV) stack is realized in commercial IGBT three phase frame. assembly comprises custom packaged single-chip half bridge modules, gate driver units very low isolation capacitance, DC-link capacitors, busbar and liquid cooled heatsink. designed stacks are tested DC-fed back-to-back setup total circulated 42 kVA, 6 kV, rms load current...

10.1109/apec39645.2020.9124441 article EN 2022 IEEE Applied Power Electronics Conference and Exposition (APEC) 2020-03-01

This letter proposes a behavioral model for analyzing the ground current in medium-voltage (MV) inductors. The impedance between terminals and connection of inductors is measured by analyzer, which capacitive at low frequency. In order to characterize this impedance, multistage paralleled RLC circuit proposed. An analytical method further developed calculate parameters proposed equivalent circuit, enables predict time-domain response MV A digital twin double-pulse-test setup LTspice, where...

10.1109/tpel.2020.3010103 article EN IEEE Transactions on Power Electronics 2020-07-17

This article characterizes three parasitic capacitances in copper-foiled medium-voltage inductors. It is found that the conventional modeling method overlooks effect of fringe field, which leads to inaccurate To address this problem, contributed by electrical field identified first, and a physics-based analytical for proposed, avoids using any empirical equations. The total are then derived different cases with core potentials, from three-terminal equivalent circuit derived, thus, inductors...

10.1109/tpel.2020.3048226 article EN IEEE Transactions on Power Electronics 2020-12-30

It is commonly assumed that power semiconductor switching losses are the same for high-side and low-side devices in a half-bridge module. However, this paper reveal SiC MOSFET medium voltage module exhibits over 40 % higher energy compared to MOSFET. The loss imbalance attributed parasitic gate capacitance module, which contributes equivalent Miller capacitance. A physics-based dissipation model therefore proposed, distinguishing between dissipation. Double pulse testing demonstrates...

10.1109/tpel.2024.3368115 article EN IEEE Transactions on Power Electronics 2024-02-21

This paper proposes a physics-level modeling method for analyzing the primary to secondary-side (common-mode) parasitic capacitance of transformer Medium-voltage SiC MOSFETs gate drivers. The lumped circuit-based physics-model turn-to-turn capacitance, turn-to-core and self core are derived, it is found that mainly contributes total equivalent common-mode capacitance. measured impedance shows high agreements with calculated value, where accuracy proposed can be proved based on experimental results.

10.1109/iecon.2019.8926673 article EN IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society 2019-10-01

Advances in high breakdown voltage SiC MOSFETs allows design of medium power modules with simpler topologies, however, dv/dt addition to di/dt makes parasitics more important consider loss estimations. Correct estimations can help prevent costly and time-consuming problems a process. Data sheet values be used directly for estimation, but detailed approaches using device-level SPICE model fitting inclusion module will give estimation may predict transient behavior at cost increased...

10.1109/ecce.2019.8913066 article EN 2022 IEEE Energy Conversion Congress and Exposition (ECCE) 2019-09-01

In high-power medium-voltage applications, inductors usually have multiple windings on a single core, due to the high inductance value and current stress. The coils are electronically connected in either series or parallel, with considerations of loss cost. However, differences parasitic capacitance using parallel connections not discussed. Therefore, this article reveals that comparison for windings, utilizing connection winding can significantly reduce multiwindings without sacrificing...

10.1109/tpel.2022.3187449 article EN cc-by-nc-nd IEEE Transactions on Power Electronics 2022-06-30

Sustained Miller region oscillations are observed during turn-on of the high-side SiC MOSFET in a half-bridge 10kV power module double pulse testing at 6kV, 70A. The analyzed and cause is identified as positive feedback loop forming between common source inductance equivalent capacitance, with current path through parasitic capacitive couplings grounded baseplate. Using custom manufactured prototype medium voltage modules experimentally validated mitigation strategy proposed, demonstrating...

10.23919/epe23ecceeurope58414.2023.10264475 article EN 2023-09-04

Capacitive parasitic couplings in power electronics systems are gaining increased attention due to the emergence of wide bandgap devices, with main challenges being faster switching speeds and operating voltage capabilities causing slew rate (dv/dt). The high dv/dt induces capacitive displacement currents through channel semiconductor effectively reducing speed, resulting an increase Volt-Ampere integral, incurring surplus energy dissipation. This paper highlights that module gate side...

10.1109/cieec58067.2023.10165973 article EN 2022 IEEE 5th International Electrical and Energy Conference (CIEEC) 2023-05-12

The isolated gate-driver power supply is one of the crucial components inside medium-voltage (MV) converter, which provides galvanic isolation featuring low common-mode (CM) capacitance and high dv/dt immunity. Therefore, design transformer needs to be customized. However, none known papers have proposed a convenient assembly method. For this purpose, an easy-to-manufactured planar for MV in paper. designed has been tested at 7 kV DC voltage measured CM 0.628 pF. Thus, capability...

10.1109/pedg56097.2023.10215259 article EN 2022 IEEE 13th International Symposium on Power Electronics for Distributed Generation Systems (PEDG) 2023-06-09

This paper highlights the increased importance of volt-second compensating converter non-linearities such as dead time for wide bandgap semi-conductor devices utilized in medium voltage converters. The increasing level converters impose a penalty to compensation required compensate error caused by time. A thorough analysis and experimental results switching events are present 10 kV silicon-carbide MOSFET power module.

10.23919/epe23ecceeurope58414.2023.10264515 article EN 2023-09-04

This paper analyzes the phenomenon of ground current in filter inductors (with a grounded core/frame) medium-voltage (MV) SiC-MOSFET-based. The inductor is generated during switching transients, due to capacitive coupling between winding and core/frame. A general three-terminal equivalent circuit proposed for representing couplings inductors, which allows extraction admittances terminals by using system identification tool, thus can be accurately simulated frequency range concern (up 100 MHz...

10.1109/apec39645.2020.9124147 article EN 2022 IEEE Applied Power Electronics Conference and Exposition (APEC) 2020-03-01

The structural optimization of power modules for reliability can be performed without physical prototyping if the weakness in assessed on a 3D model. In this study, thermal stress simulation is investigated as predictive tool heat cycle test (R CT) failure point medium voltage module. module has multi- layer structure two different ceramics (A12O3 and AIN) to reduce parasitic capacitance. complex structured module, actual samples are shown coincide with points thermo-mechanical simulation....

10.1109/apec43580.2023.10131157 article EN 2022 IEEE Applied Power Electronics Conference and Exposition (APEC) 2023-03-19

Thermal simulations evaluated temperature distribution of 10kV and 15kV SiC-MOSFETs with larger die edge areas. Experimental measurements the surface confirmed thermal modeling. The results revealed that edges amplified variation compared to 1.2kV SiC-MOSFET. Simulation also mentioned bond wires solder during power cycle testing.

10.23919/epe23ecceeurope58414.2023.10264610 article EN 2023-09-04

In this paper, the capacitive couplings between terminals and magnetic core of a medium-voltage (MV) filter inductor are identified by using double-pulse-test setup under high-voltage -current excitation, instead traditional impedance analyzer, which performs frequency sweep at low-voltage magnitudes. The time-domain current voltage waveforms from measured further converted into frequency-domain signals Fourier Transformation. From this, terminal-to-core MV inductors saturation is obtained....

10.1109/compel49091.2020.9265854 article EN 2020-11-09

This paper characterizes three parasitic capacitances in copper-foiled medium-voltage inductors. It is found that the conventional modeling method overlooks effect of fringe field, which leads to inaccurate To address this problem, contributed by field identified first, and a physics-based analytical for proposed, avoids using any empirical equations. The total are then derived different cases with core potentials, from three-terminal equivalent circuit derived, thus, inductors explicitly...

10.36227/techrxiv.13338053.v1 preprint EN cc-by-nc-sa 2020-12-07
Coming Soon ...