A5047256160- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- CCD and CMOS Imaging Sensors
- Semiconductor materials and devices
- Analytical Chemistry and Sensors
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Photonic and Optical Devices
- ECG Monitoring and Analysis
- Power Line Communications and Noise
- Sensor Technology and Measurement Systems
- Semiconductor Lasers and Optical Devices
- Quantum-Dot Cellular Automata
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
Xidian University
2018-2025
This paper introduces a dual main clock generator (DMCG) and digital serializer (DS) to improve the power efficiency of time-interleaving (TI) analog-to-digital converters (ADCs). The proposed DMCG combines dual-path front end an improved selecting signal that addresses potential phase error reduces peak current clock-driving circuits by 60%. DS is serialize outputs without employing power-hungry inverter-based buffer chains thus reducing consumption 39.2%. reference-free time skew...
This paper presents a process, voltage, and temperature (PVT)-insensitive dynamic amplifier (DA) with gain enhancement for pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The shift due to process variation is attenuated through the counteraction of input transconductance delay-based integration time. Furthermore, based on charge conservation, gain-folding technique proposed improve limit conventional DA, tripling amplitude. DA incorporated in design...
This paper presents a process, voltage and temperature (PVT) robust Gm-R-based residue amplifier (RA). The proposed folded positive feedback (FPF) technique facilitates high open-loop gain of 49.2 dB bandwidth 30.6 GHz without employing multiple cascading stages or cascode devices, consuming only 8.2 mW. PVT robustness the RA is self-adapted, addressing requirement bias-generating circuitry. Transistor level design simulations are implemented based on 28 nm CMOS process. Configured in...
Pipelined SAR ADCs have become popular due to their excellent speed, resolution, and power efficiency. In advanced processes, the single-channel pipelined ADC has gone beyond 1GS/s with $\geq$10b resolution [1–2]. The key operation in a is residue amplification (RA) which realizes transfer provides interstage gain, but it also constitutes speed bottleneck. Fig.1 (top) depicts typical time allocation of three-stage architecture that widely adopted achieve both high speed. current next stages...
lnternet-of-Things (1oT) devices, powered by common 1.5V-to-3.6V batteries, generally require low power and less-than-l% inaccuracy frequency references for wake-up. As the mainstream of on-chip references, RC oscillators have shown excellent temperature coefficients (TC <10ppm$/^{\circ}$C), but they usually come at expense time-consuming multi-point trimming [1,3], tens-of-pJ/cycle energy efficiency [3], or large area [4]. A compact oscillator [2] has achieved an sub-pJ/cycle, its line...
A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, proposed achieves 99.09% 93.41% reductions average energy area, respectively, over conventional scheme. Moreover, SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) 0.160 LSB consumes zero reset energy.