A5100635138- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- CCD and CMOS Imaging Sensors
- Low-power high-performance VLSI design
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- VLSI and FPGA Design Techniques
- Neuroscience and Neural Engineering
- Sensor Technology and Measurement Systems
- Advanced MEMS and NEMS Technologies
- Semiconductor materials and devices
- Mechanical and Optical Resonators
- Advanced Memory and Neural Computing
- Photonic and Optical Devices
- Electromagnetic Compatibility and Noise Suppression
- Microwave Engineering and Waveguides
- Semiconductor Lasers and Optical Devices
- Smart Grid Security and Resilience
- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Tunneling and Rock Mechanics
- Orthopedic Infections and Treatments
- Orthopaedic implants and arthroplasty
- Optical Network Technologies
- Advanced DC-DC Converters
Xidian University
2016-2025
Heilongjiang Provincial Academy of Agricultural Sciences
2025
Donghua University
2024
American Health Network
2022-2023
Antea Group (France)
2023
Institute of Electrical and Electronics Engineers
2022-2023
Ministry of Education of the People's Republic of China
2023
Canadian Standards Association
2022
University of Science and Technology of China
2014-2021
China University of Petroleum, East China
2020
This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of linearity on DAC size ADC, background mismatch calibration technique is employed. As result, thermal noise will be major constraint size. In addition, compact noise-reduction proposed to alleviate adverse impact input-referred comparator effective resolution. Moreover, 2.5-V on-chip LDO, which serves as reference generator core, also...
A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. novel switching scheme (COSS) proposed to reduce the power consumption matching requirement for capacitors ADCs. The (including reset energy), total capacitance static performance (INL & DNL) of are reduced by 98.08%, 75%, respectively, compared conventional architecture. Based on analysis non-linear errors caused comparator input parasitic capacitance, an improved push-pull pre-amplifier...
This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. Different from most prior works adopting cascaded integrator feed-forward (CIFF) structure, proposed architecture employs unity-gain buffer delay elements operated in ping-pong manner to perform EF function. Since lossless residue extraction summation, it exhibits high efficiency realizing strong (NS) effect....
An asynchronous successive approximation register analog-to-digital converter (ADC) for wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s 10-b, 40-MS/s 11-b, or 20-MS/s 12-b converter. Time-interleaved technique applied to expand sampling bandwidth exponentially while resolution scales down. channel mismatches are cancelled by the digital calibration technique. bulk-biasing used in switch reduce influence of charge injection caused top-plate sampling. In...
This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of capacitively-coupled instrumentation amplifier (CCIA) and 16-bit delta-sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta$</tex-math> </inline-formula>...
Background: As a major food crop, maize is highly susceptible to pathogenic bacteria, which greatly reduces its yield and quality. Metabolomics reveals physiological biochemical changes in organisms aids analyzing metabolic caused by various factors. Methods: This study utilized metabolomics examine maize’s after NCLB infestation, aiming uncover related pathways potential biomarkers. The metabolite measurements were performed during the silking stage. Results: PCA showed an obvious...
This work presents an ultralow-power 10-bit 200-kS/s single-ended successive approximation register (SAR) analog-to-digital converter (ADC) for implantable biosensor applications. A high energy- and area-efficient switching scheme is proposed, which realizes 95.4% energy saving in a digital-to-analog (DAC) two times DAC area reduction compared to the conventional SAR ADC. The common-mode variation proposed input-independent, resulting reduced dynamic offset harmonic distortion. Besides, low...
MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than close-loop to achieve low power consumption. In structure, voltage control readout technique preferred cost. However, suffers from poor noise performance and efficiency (in terms FoM). this paper, weak feedback oversampling successive approximation circuit which merges closed-loop hybrid dynamic amplifier reduction proposed floor, high accuracy. The WFB-OSA based...
The observed Raman spectra for single crystals of rubrene and tetracene are compared with the calculated isolated molecules. measurements presented bulk properties material, they confirmed that vapour growth process yields very pure, unstrained crystals. Finally, indicate rubrene, unlike many other oligoacenes, has weak intermolecular coupling no observable vibrational modes. We discuss apparent conflict between high mobility π-electron overlap in this material.
This brief presents a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with lossless integrator for achieving low power and high NS efficiency. It implements the through ping-pong structure low-gain dynamic amplifier moderate gain variation tolerance. Taking advantage of integrator, resolution SAR ADC is allowed under same quantization...
This work presents an always-on reference ripple cancellation technique that actively cancels the settling error throughout entire SAR conversion process. Unlike conventional designs require high-speed buffers or large on-chip decoupling capacitors to minimize error, it incorporates extra path cancel which can provide considerable tolerance, thus significantly relaxing requirement. To verify proposed technique, a prototype 10-bit 100-MS/s ADC is fabricated in 40-nm CMOS Equipped with only...
MEMS capacitive accelerometer for the Internet of things applications is designed with open-loop structure rather than close-loop to achieve low power consumption. In structure, voltage control readout instead charge preferred cost. However, suffers from efficiency (in terms <i>FoM</i>) due significant parasitic-capacitance-induced noise. this paper, correlated double amplifying (CDA) technique proposed reduce noise circuit high efficiency. Although, traditional sampling (CDS) can also be...
This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to time domain, compact interpolation-based time-to-digital (TDC) resolves 4-bit in each SAR cycle with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times $ </tex-math></inline-formula> linear TD interpolation. scaling-friendly...
This paper introduces a dual main clock generator (DMCG) and digital serializer (DS) to improve the power efficiency of time-interleaving (TI) analog-to-digital converters (ADCs). The proposed DMCG combines dual-path front end an improved selecting signal that addresses potential phase error reduces peak current clock-driving circuits by 60%. DS is serialize outputs without employing power-hungry inverter-based buffer chains thus reducing consumption 39.2%. reference-free time skew...
This paper presents a process, voltage, and temperature (PVT)-insensitive dynamic amplifier (DA) with gain enhancement for pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The shift due to process variation is attenuated through the counteraction of input transconductance delay-based integration time. Furthermore, based on charge conservation, gain-folding technique proposed improve limit conventional DA, tripling amplitude. DA incorporated in design...