Gating of the outputs a portion scan cells (partial gating) has been recently proposed as method for reducing dynamic power dissipation during scan-based testing. We present new systematic selecting, under area and performance design constraints, most suitable gating subset well proper value each one them, aiming at reduction average switching activity show that outperforms corresponding already known methods, with respect to reduction.

Built-in self-test (BIST) is an effective approach for testing large and complex circuits. When BIST used, a test pattern generator (TPG), response verifier controller accompany the circuit under (CUT) in chip, creating self-testable circuit. In this paper we propose new algorithm seeds selection LFSR (linear feedback shift register) based test-per-clock BIST. The proposed uses well-known concept of solving systems linear equations and, on heuristics, minimizes number vectors while achieving...

Image edge detection plays a fundamental role in image processing as well computer and machine vision while when applied medical images can improve diagnosis. Thus, efficient hardware implementation of an system is highly appreciated. In this work we propose novel architecture for filtering using the Residue Number System (RNS). A VLSI proposed dictates that employment RNS arithmetic leads to small complexity high operation frequency.

Power dissipation during scan-based testing has gained significant importance in the past few years. In this work we examine use of transition frequency based on scan cell ordering techniques pseudorandom BIST order to reduce average power dissipation. We also propose resetting input register circuit together with its elements further Experimental results indicate that proposed can up 57.7%.

It is shown that a diminished-1 adder, with minor modifications, can be also used for the modulo 2 n + 1 addition of two n-bit operands in weighted representation, if sum its input decreased by one. This modified adder perform less area and time than solutions are based on use binary adders and/or adders. Therefore, it applied effectively to all arithmetic components finally derive addends. A small number have past adopted such scheme without presenting this general theory. By applying idea,...

Presents a new reseeding technique for LFSR-based test pattern generation suitable circuits with random-pattern resistant faults. Our eliminates the need of ROM storing seeds since LFSR jumps from state to required (seed) by inverting logic value some bits its next state. An efficient algorithm selecting points is also presented, which targets complete fault coverage and minimization cardinality set hardware implementation generator. The application proposed ISCAS '85 combinational part '89...

Shifter circuits are introduced for residue number systems (RNS) with bases composed of the moduli set {2n+1, 2n, 2n−1}. The proposed straightforward to design and their implementation has very small area delay, making shift operations in RNS inexpensive.

The contribution of this paper is twofold. We firstly show that an augmented diminished-1 adder can be used for the modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> +1 addition two n-bit operands in weighted representation, if it driven by whose sum has been decreased 1. This scheme outperforms solutions are based on use binary adders and/or + 1 both area and delay terms. then apply design residue generators (RGs) multi-operand...

Multi-moduli architectures are very useful for reconfigurable digital processors and fault-tolerant systems that based on the Residue Number System (RNS). In this paper we propose two multi-moduli squaring support most common moduli cases in RNS channels, is, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -1, +1. The proposed modified Booth encoding of input operand deriving required partial products Dadda adder trees their addition....

One of several approaches for designing highly-reliable systems relies on using error detecting codes (EDCs) and implementing digital circuits as self-checking. class EDCs that has been very often used to implement self-checking are Berger codes. Although self-testing checkers (STCs) have proposed in the past, they mostly present area delay results based gate counts levels not real implementations. In this work we consider implementations evaluate area, power characteristics STCs modified...

In this paper we show that an accumulator can be modified to behave as a Non-Linear Feedback Shift Register suitable for test response compaction. The hardware required modification is less than modify register Multiple Input Linear Register, MISR. We with experiments on ISCAS'85, ISCAS'89 benchmark circuits and various types of multipliers the post-compaction fault coverage obtained by proposed scheme higher already known based compaction schemes in most cases identical achieved using

This paper presents a novel test vector ordering method for average power consumption minimization. The proposed orders the vectors taking into account expected switching activity at primary inputs and very small set of internal lines circuit under test. computational time required by is while reduction achieved close to best, with respect reduction, most time-consuming method. Experimental results show that apart from achieves significant peak too.

The diminished-one encoding is often considered when representing the operands in modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> +1 channels of a Residue Number System (RNS) since it can offer increased arithmetic processing speed. However, limited research available on design residue-to-binary (reverse) converters for RNSs that use one or more channels. In this paper we introduce simple methodology designing such which be...

The diminished-one representation has been proposed for RNS-based systems with moduli of the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> +1 forms as an encoding that is more efficient than normal in arithmetic processing units. However, its use necessitates a two-step reverse conversion, which diminished-to-normal conversion first performed before final residue-to-binary resulting performance loss. In this paper we introduce modulo...

The low power as a feature of BIST scheme is significant target due to quality well cost related issues. In this paper we examine the testability multipliers based on Booth encoding and Wallace tree summation partial products present methodology for deriving Built Self Test (BIST) them. We propose several design rules designing in order be fully testable under cell fault model. proposed derived achieved by: (a) introducing suitable Pattern Generators (TPG); (b) properly assigning TPG outputs...

A new architecture for modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> +1 multi-operand addition (MOMA) of weighted operands is introduced. It based on the use a translator circuit that enables to n-bit operations performing addition. Our experimental results indicate proposed MOMAs offer significant savings in execution time compared previously solutions either require two parallel additions or carry-save adder tree with twice...

Aiming at low power dissipation during testing, in this paper we present a methodology for deriving novel BIST scheme modified Booth multipliers. Reduction of the is achieved by: (a) introducing suitable test pattern generator (TPG) built 4-bit binary and Gray counter, (b) properly assigning TPG outputs to multiplier inputs (c) significantly reducing set length. The reduction total from 44.1% 54.9%, average per vector 21.4% 36.5% while peaks 15.8% 34.3%, depending on implementation basic...

Test vector ordering with repetition has been presented as a method to reduce the average well peak power dissipation of circuit during testing. Based on this method, in paper we present some techniques that can be used further dissipation. Experimental results validate proposed achieve considerable savings energy and while reducing length resulting test sequences compared original method.