ABSTRACT This paper presents a single‐channel, 12‐bit, 80‐MS/s SAR‐assisted pipelined ADC. A ring amplifier is used as the inter‐stage residue amplifier, employing dynamic biasing to enhance PVT stability. Additionally, drain‐source voltage of MOS transistor utilized generate dead‐zone voltage, which reduces impact on secondary pole frequency and further improves non‐binary weighted capacitor array employed in two‐stage sub‐ADC provide redundancy, reduce settling time, improve speed, work...

Circularly-polarized (CP) patch antennas with enhanced bandwidth based on capacitively coupled orthogonal radiators are proposed. Several alternately arranged one by along the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${x}$ </tex-math></inline-formula> - and notation="LaTeX">${y}$ -direction, producing currents far fields. The adjacent to each other coupling structure not only contributes power...

Balance among inter-spike interval (ISI), power consumption and biological reality is one of the major concerns Hodgkin-Huxley neuron circuit design trade-off. This paper proposed a CMOS high-speed H–H design. The three current channels in theoretical model were achieved by 180-nm circuits. For accurate measurement, input output modules are integrated with circuit. validation design, fabricated 1P6M process. active area about 0.018 mm2. With 1.8 V input, around 111.3 μW. Test results have...

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters a fully integrated fractional-N synthesizer is presented. Implemented in standard 0.5-/spl mu/m process without any off-chip component, the complete has measured image rejection of 79 dB, sensitivity -90 dBm, an IIP3 -24 noise figure 22 dB power 227 mW chip area 5.7 mm/sup 2/. The achieves phase -118 dBc/Hz at 600 kHz offset settling time less than 150 /spl mu/s.

This communication presents a compact normal-mode hybrid-helix antenna of circular polarization and its Yagi array configuration. By cascading two types helices with different turn spacings radii, the element effectively alleviates limitation traditional helix that is challenging to simultaneously achieve high radiation efficiency. The proposed hybrid also further extended for obtain endfire polarization. For experimental verification, fabricated using selective laser melting (SLM)...

A planar dual-band dual-sense circularly polarized (CP) microstrip array is proposed. This implemented on a single-layer substrate and easily extended to the design of larger array. new antenna element exploited by symmetrically placing nonradiative resonators four side edges square patch. quantitative method proposed based equivalent circuit model element. For given two operating frequencies, required parameters patch can be calculated. Theoretical magnitude ratio phase difference responses...

This letter reports a transformer-feedback voltage-controlled oscillator (VCO) (TF-VCO) with separated differential-mode (DM) and common-mode (CM) resonance for feasibility low phase noise. With an effort to isolate the DM CM resonances by relatively resonance-independent single-ended (SE) capacitors connected at NMOS source tuning cancellation transformer between drain source, proposed VCO achieves resonant frequency interaction resonances. A factor <inline-formula...

An active-integrated antenna (AIA) system with a compact and scalable topology is proposed in this work. Two kinds of highly integrated AIA unit cells, i.e., the oscillating cell amplifying cell, are designed by integrating active switching circuits into modified monopole antennas. In each working cycle, remains stable until it triggered radiation wave from for in-phase radiation, thereby output power. order to reduce spacing, corners ground antennas cut off threshold voltage cells precisely...

A 70-MHz VGA with a 70-dB gain control range is designed using 0.5-/spl mu/m CMOS process. The employs an automatic continuous-time offset cancellation and can tolerate input voltage up to 50 mV. power consumption 15 mW from 2.5-V supply, the core area 400/spl times/240 /spl mu/m/sup 2/.

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band and out-of-band are both reduced due to the time-amplifying technique class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) used here guarantee reference spur. proposed PLL fabricated 65-nm CMOS mixed-signal process an area of 0.220 mm2, clock 150 MHz. measurement results show that...

A fully-integrated 950-MHz bandpass amplifier for use in a wireless receiver is designed standard 0.5-/spl mu/m CMOS process. Q-compensation circuit embedded to achieve desired bandwidth of 25 MHz. Unbalanced g/sub m/-cells are used maximize the linearity. notch filter adopted an image rejection 50 dB. switchable-capacitor array tune center frequency over 100 MHz range. The measures gain 22 dB with IIP3 -17 dBm, noise figure 10 and draws current mA from 2-V supply.

A low power small area electrical backplane equalizer using programmable analog zeros and folded active inductors is presented in this paper. The circuit was implemented a 1.0-V TSMC 90nm CMOS process. With one zero stage, the occupies only 0.015mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip dissipates 8mW power. At 3.125Gb/s data rate, lab measurement shows that provides 6.5dB gain boost at baud-rate frequency. Without use of...