Jaehyeon So

ORCID: 0009-0004-7133-3205
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About
Contact & Profiles
Research Areas
  • Hand Gesture Recognition Systems
  • Advanced Optical Sensing Technologies
  • Embedded Systems Design Techniques
  • Antenna Design and Optimization
  • DNA and Biological Computing
  • Optical Coherence Tomography Applications
  • Power Systems and Technologies
  • ECG Monitoring and Analysis
  • Advanced Computational Techniques and Applications
  • Interconnection Networks and Systems
  • Energy Harvesting in Wireless Networks
  • Advanced Data Storage Technologies
  • Human Pose and Action Recognition
  • Virtual Reality Applications and Impacts
  • Optical Imaging and Spectroscopy Techniques
  • Image and Video Stabilization
  • Algorithms and Data Compression

Sungkyunkwan University
2022-2024

With the recent prominence of artificial intelligence (AI) technology, various research outcomes and applications in field image recognition processing utilizing AI have been continuously emerging. In particular, domain object using 3D time-of-flight (ToF) sensors has actively researched, often conjunction with augmented reality (AR) virtual (VR). However, for more precise analysis, high-quality images are required, necessitating significantly larger parameters computations. These...

10.3390/s24216918 article EN cc-by Sensors 2024-10-28

Top- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$K$</tex> Sorting is a widely used technique for se-lecting the largest or smallest numbers from input elements. In this paper, we present an efficient low-power and flexible top-K sorting architecture with cell gating on field-programmable gate arrays (FPGAs). Our consists of data filter unit, counter, L-cascaded cells, where unit allows users to select user-defined values sort, counter by...

10.1109/mwscas57524.2023.10406121 article EN 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) 2023-08-06

Systolic array (SA) architectures have been widely employed in deep learning accelerators with their high computation efficiency. However, the fixed SA structure leads to inefficiency performance and power when computing variable input dimension precision. To resolve this drawback, work proposes a flexible systolic architecture data precision (PD-FSA) that can compute layers less cycles. By calculating minimum cycles required for layers, proposed avoid unnecessary We also propose control...

10.1109/isocc56007.2022.10031594 article EN 2022 19th International SoC Design Conference (ISOCC) 2022-10-19
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