Owing to the breakthrough of artificial meta-materials, emergence and evolution reconfigurable intelligent surface (RIS) have drawn a novel blueprint for development sixth-generation (6G) wireless networks, through creation smart radio environment meet requirement ubiquitous connectivity. Meanwhile, vision 6G illuminates integration sensing communication, bringing out demand both high-quality communication high-precision localization. Therefore, regarding future localization, potential RIS...

A configurable IPSec processor for a high performance in-line network security that integrates two embedded 32-bit CPU cores, and an protocol on SoC is presented. The can implement the transport/tunnel mode AH ESP of IPSec, support AES-128/192/256, HMAC-SHA-1 algorithm. number AH, ESP, AES, IP-cores in design be configured different use such as 10 Gigabit Ethernet Ethernet, even next generation 40/100G Network. Low power also considered design. In processor, crossbar switch architecture...

The IP security protocol (IPSec) is an important and widely used in the layer. But implementation of IPSec a computing intensive work which greatly limits performance high speed network. In this paper, accelerator 10Gbps in-line network processor (NSP) presented. design integrates processing cryptographic processing; transport/tunnel mode AH, ESP protocols AES, HMAC-SHA-1 algorithms are realized by hardware. An efficient partial crossbar data transfer skeleton with iSLIP scheduling algorithm...

Purpose The current popular image processing technologies based on convolutional neural network have the characteristics of large computation, high storage cost and low accuracy for tiny defect detection, which is contrary to real-time accuracy, limited computing resources required by industrial applications. Therefore, an improved YOLOv4 named as YOLOv4-Defect proposed aim solve above problems. Design/methodology/approach On one hand, this study performs multi-dimensional compression...

10Gbps Ethernet Security Processor is very important in future network telecommunication. In order to meet the performance of ultra high throughput ESP, An architecture multiple SHA-1 IP cores paralleled based crossbar switch are proposed this paper. Firstly, throughput, low power consumption algorithm IP-core designed, then, an effective scheduling with our simulation SMIC 65nm, single core could reach 4.27Gbps frequency 400Mhz. Verification on Xilinx Virtex FPGA, 1943 slices LUTs used for...

This paper presents design and verification of a 10Gbps in-line Network Security Processor (NSP) with single 32-bit embedded CPU. NSP is designed to process the IPSec protocol at line speed for Ethernet. SerDes, processing module, database query CPU are be integrated on one chip form System Chip (SOC). The used OR1200, open source general-purpose Harvard Microarchitecture. acts as controller, bringing flexibility scalability system. Virtex-5 XC5VXS95T FPGA board in verification.

This paper deals with an in-line network security processor (NSP) design that implements the Internet Protocol Security (IPSec) protocol processing for 10 Gbps Ethernet. The high speed data transfer, IPSec including crypto-operation, database query, and header are integrated in design. NSP is implemented using 65 nm CMOS technology layout area 2.5 mm×3 mm 360 million gates. A configurable crossbar transfer skeleton implementing iSLIP scheduling algorithm proposed, which enables simultaneous...

Design of an IPSec (Internet Protocol Security) IP-Core for 10 Gigabit Ethernet Security Processor is presented in this paper. The highest data throughput one can achieve 1.5Gbps. With parallel 8 IP-Cores, design 10Gbps process and fulfill a requirement. low power dissipation also used the to reduce dissipation.

Abstract In the era of big data, network data will increase dramatically, which face great security work. With growth geometric multiple, we a variety problems. Through computer technology, can guarantee environment, play an important role in protecting massive information. have greatly expanded functions Internet, improves transmission speed. First, this paper analyzes problem security. Then, puts forward methods.

In this paper, the elasto-plastic dynamic analysis on failure behaviors of steel double-layer grids supported by tridimensional truss columns used in a gymnasium with function earthquake victims shelter under disaster is carried out EL-centro wave SAP2000, and appraisal results their anti-failure performances are presented strong action based plastic-hinge theory. analyses, geometric material nonlinear effects considered simultaneously The plastic development level rod, deformed shape type...

Design of a Gigabit In-Line scalable Network Security Processor on one chip is presented. With 8 parallel chips array and some control logic, the design may be used in 10 Ethernet. Moreover, custom-specific off-chip crypto algorithms can replace standard through pr-reserved data interface, which improves scalability operation.

Traditional experimental verification for nonlinear system identification often faces the problem of experiment model repeatability. In our research, a steel frame is developed to imitate behavior single story under horizontal excitation. Two adjustable rotational dampers are used simulate plastic hinge effect damaged beam-column joint. This suggested as benchmark dynamics study. Since form provided by damper unknown, Morlet wavelet based method introduced identify mathematical this...

This paper presents a new realization method of broadband power amplifier based on novel filter matching network. The network band-pass has an excellent frequency-selection function, which can ensure the characteristics in aim band and generates out-of-band harmonic suppression. Finally, we manufactured measured it. saturated output is greater than 40 dBm range 1 to 3 GHz, limited ±1.5 dB gain flatness, rejection stronger −20 dBc.

In applications based on Si/SiGe HBTs, the veracity of AC equivalent circuit model is key element during design. To avoid errors in available ranges for bipolar devices from f/sub /spl beta// to T/, we developed a novel with accurate form by derivation I-V equations and descriptions Y H type parameters. The HBTs' represents Delta/E/sub g/ between two sides heterojunction, legible differences BJTs capacitance proportion caused decreasement emitter base doping rate ratio resistance reduction...