A5050178022- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Analog and Mixed-Signal Circuit Design
- Silicon Carbide Semiconductor Technologies
- Health and Wellbeing Research
- Radio Frequency Integrated Circuit Design
- Electrostatic Discharge in Electronics
- Neuroscience and Neural Engineering
- Mental Health Treatment and Access
- Additive Manufacturing and 3D Printing Technologies
- Superconducting and THz Device Technology
- Suicide and Self-Harm Studies
- Stroke Rehabilitation and Recovery
- Balance, Gait, and Falls Prevention
- Nanomaterials and Printing Technologies
- Mechanical and Optical Resonators
- Advanced Sensor and Energy Harvesting Materials
- Semiconductor Quantum Structures and Devices
- Advanced MEMS and NEMS Technologies
Jeonbuk National University
2023
United Microelectronics (Taiwan)
1994-2009
United Microelectronics (United States)
2009
University of Oulu
2005
National Yang Ming Chiao Tung University
2002
A low-voltage low-power signal processing chip for electrocardiogram measurements has been designed and manufactured. The circuit includes a continuous time, offset-compensated preamplifier with an amplification of 40 dB, eighth-order Butterworth switched-opamp switched-capacitor (SO-SC) filter passband 8-30 Hz, 32-kHz crystal oscillator, SO-SC postamplifier, bias circuit. whole operates supply voltages from 1.0 to 1.8 V the measured average current consumption is only about 3 /spl mu/A....
An investigation is conducted of mismatching properties after channel hot carrier (CHC) and negative bias temperature instability (NBTI) stress observed using pMOSFETs various device sizes from 90 nm CMOS technology. The purpose this study to analyse the transistor pairs foregoing reliability tests. Degradations are extracted by measuring variations Vtlin Idsat before stress. experiments show that CHC mode more serious than NBTI mode. probable mechanism mismatches due random generation traps...
The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p/sup +/ poly-gate PMOSFET's. RSCE found to be more significant as boron penetration becomes severe. in BF/sub 2/ doped poly-gated MOS devices and alleviated buffered devices. Fluorine enhanced diffusion gate oxide during high temperature process believed account RSCE, which also confirmed by using a two-dimensional simulator.< <ETX...
In this letter, we demonstrate a high-performance gate-assisted junction varactor. The gate plays an important role in the varactor; it can decrease series resistance and enlarge capacitance of device. With assistance positive-biased gate, Q-factor varactor with 723 fF at 2.4 GHz is as high 108. Its tuning ratio 30.1% when operated range 0.5 to 2.5 V.
Differential inductors have significant advantages over single-end inductors. But the conventional differential are not really symmetrical in geometry. Here, we present a novel inductor that is fully its layout. Some measurement data will be shown to prove it.
In this report, hot carrier stress impact on mismatch properties of n and p MOS transistors with different sizes produced using 0.15 /spl mu/m CMOS technology is presented for the first time. The research reveals that HCI does degrade matching nMOSFETs' properties, but, pMOSFETs, changes are minor. Due to variation after stress, analog circuits' parameters, it found lines pMOSFETs exhibit cross points both sigma/ (/spl square/ V/sub t,op/) square/I/sub ds,op//I/sub ds,op/) drawings. It...
In this report, nMOSFETs having 20 Aring and 32 gate oxide thickness of 0.13 mum technology are used to investigate DC hot carrier reliability at elevated temperatures up 125degC. The research also focused on the degradation analog properties after injection. Based results experiments, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d,op</sub> (defined based application) is found be worst case from room temperature This result should a...
A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structure is proposed. Experimental results show that it can successfully provide for negative and positive with failure thresholds greater than +or-1 kV +or-10 in machine-mode (MM) human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages both SCRs be readily achieved without involving device or junction breakdown.< <ETX...
Purpose: The aim of the study was to investigate effects a mindfulness-based stress reduction program on perceived stress, internalized stigma, and psychological well-being psychiatric inpatients. Methods: A non-equivalent control group with pretest-posttest design used. Participants were obtained from closed wards hospital in K-city. total 45 people included this study, 22 experimental 23 group. pre, post, follow-up scores both groups using Korea Perceived Stress Scale, Internalized Stigma...
A new on-chip ESD protection circuit with complementary SCR structures is proposed. This can provide above /spl plusmn/6500 V and plusmn/400 in human-body-mode machine-mode stresses, respectively, the total layout area of 108 mu/m/spl times/242 mu/m including latchup guard-ring 10-/spl width a 90 times/90 metal pad for wire bonding.
It is well-known that the important reliability issues include drain avalanche hot-carrier (DAHC), channel (CHC), and negative bias temperature instability (NBTI). Early researches reported pMOSFETs showed worst degradation at DAHC room if cryogenic operation unnecessary [1-2], but, based on 0.13 µm technology, our recent study case of HC has switched from to CHC low high temperature. And mechanisms pMOSFETs’ are related (BTI) effect plus reverse [3-4]. Presently, NBTI-induced pMOSFET...