In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of FBFET. The FBFET has an extremely low sub-threshold slope less than 2.3 mV/dec off-current. also propose analog integrated-and-fire neuron circuit incorporating FBFET, which significantly reduces power dissipation hardware neural networks. conventional using membrane capacitor to integrate input pulses, most energy is consumed...

We perform a system-level simulation of hardware spiking neural network (SNN) consisting silicon-based synaptic transistors and integrate-and-fire (I&F) neuron circuits. Using electrical models the device I&F circuit, three-layer fully connected SNN in is presented for MNIST pattern recognition by means ex situ training. Right-justified rate coding employed as an information encoding method, negative weight values are implemented pair (specifically, excitatory inhibitory synapses)....

We have developed a capacitor-less I&F neuron circuit with dual gate positive feedback fieldeffect transistor (FBFET) and successfully co-integrated FBFET CMOS in wafer. By implementing the FBFET, we can overcome limits of conventional CMOS, reduce energy consumption, imitate biological neuron. The floating body replace membrane capacitor that occupies large area performs leaky integration Due to extremely low sub-threshold swing (less than 0.528mv/dc), consumption is significantly reduced...

Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (Vth) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited different ways, and they have worse characteristics compared conventional NAND arrays. Technology computer-aided design simulations measurements performed to investigate mechanism cases. It found initially nonprecharged channel...

In this work, a study on semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) SFGST, poly-Si semi-floating gate (SFG) SiN charge-trap layer are utilized, respectively. When an adequate number of holes accumulated SFG, they injected into nitride by Fowler⁻Nordheim tunneling mechanism. Moreover, since SFG charged embedded field-effect...

The spiking neural network (SNN) is regarded as the third generation of an artificial (ANN). In order to realize a high-performance SNN, integrate-and-fire (I&F) neuron, one key elements in must retain overflow its membrane after firing. This paper presents analog CMOS I&F neuron circuit for retaining. Compared with conventional circuit, basic operation proposed confirmed circuit-level simulation. Furthermore, single-layer SNN simulation was also performed demonstrate effect on...

In this paper, we demonstrate retention improvement in nonvolatile charge-trapping memory cells by tunneling oxide engineering with Al2O3. By utilizing SiO2/Al2O3/SiO2 layers for the oxide, it is shown that threshold voltage window after 10 years significantly improved from 0.78 V to 4.18 through Synopsys Sentaurus technology computer-aided design simulation. addition, incorporating compared using SiO2/Si3N4/SiO2 layers. The relationship between layer thickness and trapped charge emission...

We propose a novel vector-matrix multiplication (VMM) architecture based on NAND synaptic array using pMOSFET which is an analog switch shape cell for neural network (NN) applications. A FLASH memory string consisting of and not to open string. cell's resistance can be modulated by threshold voltage (Vth) depending the amount trapped charge when input signal applies. If there no spike, turned off acts as pass gate so that only constant drop exists. Based this pair series, we confirm VMM...

In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, characteristics are analyzed. The FBFET has steep switching property low off current. We design an inverter that can power operate with FBFET. By FBFET, stand-by current is effectively suppressed in analog circuit.

We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The consists of a current mirror for spatial integration, capacitor temporal asymmetric negative positive pulse generation part, refractory finally back-propagation part learning devices. devices were fabricated using HfOx switching layer by atomic deposition (ALD). device had gradual set reset characteristics conductance was adjusted spike-timing-dependent-plasticity (STDP) rule. carried...

The rapid progress of artificial neural networks (ANN) is largely attributed to the development rectified linear unit (ReLU) activation function. However, implementation software-based ANNs, such as convolutional (CNN), within von Neumann architecture faces limitations due its sequential processing mechanism. To overcome this challenge, research on hardware neuromorphic systems based spiking (SNN) has gained significant interest. Artificial synapse, a crucial building block in these systems,...

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. top gate, which uses thin SiO₂ layer as the gate dielectric, is input terminal of transistor, receives spikes from pre-synaptic neurons. Meanwhile, nitride trapping was inserted between channel bottom to serve non-volatile memory. node that post-neuron feedback signals adjusts weight. With double-gate structure, artificial synapse can perform...

In this paper, we demonstrate the characteristics of floating body effect poly-silicon with grain boundary by SENTAURUS™ TCAD simulation. As drain voltage increases, impact ionization occurs at drain-channel junction. And these holes created are deposited on bottom to change threshold voltage. This feature, kink effect, is also observed in fully depleted silicon insulator because serve as a storage trap holes. We simulate transfer curve depending density and position boundary. The affects...

Synaptic devices store the synaptic weight in spiking neural networks (SNNs). However, because are based on memory cells, their weights vulnerable to temperature variations, which significantly degrade network accuracy. To implement temperature-robust asynchronous SNNs, neurons with captive (CSD neurons) proposed this study. Captive that mimic characteristics of located parallel integration capacitors. By using for membrane potential reset, CSD inherently equipped counteract...

A single memory cell having both volatile (VM) and nonvolatile (NVM) functions with an independent asymmetric dual-gate structure is reported, as well its programming methods. In the case of operating device a VM cell, higher sensing margin obtained, undesirable soft-programming issue suppressed when gate-induced drain leakage method used. Additionally, hold retention time operation are improved in programmed state NVM function. These results indicate that proposed has potential for...

In this paper, we investigated the dependence of minority carrier lifetime on dual gate FBFET. Generally, depending channel condition or trap density, can be degraded. Since potential barrier lowering through accumulated carriers is essential for positive feedback, deterioration make a critical influence operation device. Therefore, verified tendency threshold voltage according to and length. Through comparison with p-n diode FBFET, drew relation between voltage. As result, it has been...

In this paper, we investigate the floating body effect (FBE) in fully depleted polysilicon-body ultrathin-body MOSFETs. Generally, FBE cannot occur a body. However, demonstrate that an FBE-like phenomenon can be observed MOSFETs due to grain boundaries of polysilicon. To analyze this, devices with various conditions were fabricated and measured. As result, may argue generated holes trapped at boundaries, which causes phenomenon. Based on expect thin-polysilicon utilized for applications such...

Charge trap characteristic at tunneling oxide of floating gate NAND flash observed after program/erase (P/E) cycling. At initial P/E cycling, acceptor-like interface traps and positive are generated simultaneously but the effect is dominant consequently threshold voltage increase. However, once generated, change negligible under program or erase operation variation mainly depends on traps. Additionally, acceleration factor low extracted for relative reliability test memory devices.

In this study, we propose an analog CMOS integrate-and-fire (I & F) neuron circuit with a synaptic off-state current blocking operation. The proposed prevents unintended potential changes in the membrane capacitor owing to of devices, thereby preventing decrease accuracy spiking neural network (SNN) inference system. Compared conventional I F circuit, basic and off-current operations were confirmed circuit-level simulation. Furthermore, verify effect on network, multi-layer SNN simulation...

In this work, we developed a SPICE compact model of dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the to measurement results. We fabricated FBFET and investigated DC transient characteristics. The has an extremely low sub-threshold slope off current. operates as forward-biased PN diode after device is turned on due positive feedback loop between integrated charges potential barrier. When enough electrons are accumulated in floating body,...