A5067203106- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Parallel Computing and Optimization Techniques
- Analog and Mixed-Signal Circuit Design
- Advanced machining processes and optimization
- Advanced Surface Polishing Techniques
- Semiconductor materials and devices
- Interconnection Networks and Systems
- VLSI and Analog Circuit Testing
- Agronomic Practices and Intercropping Systems
- Radiation Effects in Electronics
- Advancements in PLL and VCO Technologies
- Embedded Systems Design Techniques
- Perovskite Materials and Applications
- Soil Carbon and Nitrogen Dynamics
- Quantum-Dot Cellular Automata
- Advanced Machining and Optimization Techniques
- Advancements in Battery Materials
- Laser Material Processing Techniques
- 2D Materials and Applications
- Legume Nitrogen Fixing Symbiosis
- Advanced Photocatalysis Techniques
- VLSI and FPGA Design Techniques
- Electromagnetic Compatibility and Noise Suppression
- Advanced Memory and Neural Computing
Sichuan University
2025
The Synergetic Innovation Center for Advanced Materials
2022-2024
Nanjing Tech University
2022-2024
Inner Mongolia Academy of Agricultural & Animal Husbandry Sciences
2022-2024
China Academy of Space Technology
2024
Harbin University of Science and Technology
2021-2024
Chapman University
2009-2023
Alibaba Group (China)
2023
Harbin Institute of Technology
2016-2018
Shenzhen Institutes of Advanced Technology
2018
In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge capture technologies. This classification is based on how to prevent or reduce redundant internal switching activities. A new flip-flop introduced: discharge (CDFF). It a technology, known as technology. CDFF not only reduces activities, but also generates less glitches at output, while maintaining negative setup time small D-to-Q delay characteristics. With data-switching...
Abstract Conventional liquid-phase methods lack precise control in synthesizing and processing materials with macroscopic sizes atomic thicknesses. Water interfaces are ubiquitous unique catalyzing many chemical reactions. However, investigations on two-dimensional (2D) related to water remain limited. Here we report the growth of millimeter-sized 2D PbI 2 single crystals at water-air interface. The mechanism is based an inherent ion-specific preference, i.e. iodine lead ions tend interface...
In a nine-year field experiment in wheat–maize–sunflower cropping system Hetao Irrigation Area, Inner Mongolia, China, organic amendments applied as straw, manure, green and the combination of manure straw increased wheat maize yield, soil aggregate stability, microbial activity comparison with chemical fertilizer, without changing greenhouse gas emission intensity.
In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The employs clock branch-sharing scheme to reduce the number of clocked transistors in design. newly proposed design also conditional discharge and split-path techniques further switching activity short-circuit currents, respectively. As compared other state art flip-flop designs, CBS_ip has an improvement up 20% 12.4% view power consumption PDP, respectively
Power consumption is a major bottleneck of system performance and listed as one the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, large portion on chip power consumed by clock which made distribution network flop-flops. this paper, various design techniques low clocking are surveyed. Among them an effective way to reduce capacity load minimizing number clocked transistors. To approach this, we propose novel pair shared flip-flop reduces local...
Charge trap materials that can store carriers efficiently and controllably are desired for memory applications. 2D promising highly compacted reliable mainly due to their ease of constructing atomically uniform interfaces, however, remain unexplored as being charge media. Here it is discovered semiconducting PbI
Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges efficient level converter with fewer and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different schemes analyzed classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor precharged style. An scheme, clocked-pseudo-NMOS (CPN) conversion presented. novel (CPN-LCFF) proposed, which combines conditional...
Due to low dielectric loss and cost, glass is developed as a promising material for advanced interposers in 2.5-D 3-D integration. In this paper, through vias (TGVs) are used implement inductors minimal footprint large quality factor. Based on the proposed physical structure, impact of various process design parameters electrical characteristics TGV investigated with electromagnetic simulator HFSS. It observed that have identical inductance larger factor comparison their silicon via...
Traditional sparse code multiple access (SCMA) systems, which transmit user codewords through fixed subcarrier allocations, exhibit vulnerability to external jamming and interference. To address this challenge, we propose a novel SCMA codebook design incorporating the frequency-hopping (FH) technique in paper. The construction of FH-SCMA codebooks is developed by applying cyclic shifting operations factor graph matrix conventional codebooks, where patterns are governed chaotic Bernoulli FH...
Flip-flops play an important role in building digital CMOS designs. Their design and optimization is critical for high-performance low power systems. In this paper, we propose flip-flops based on the explicit-pulsed flip-flop (EPFF). These new eliminate hazardous glitches associated with original EPFF output. The Static-EPFF (SEPFF) developed low-power dissipation purposes; it reduces by 13.9%-15.7%, enhances speed 4.86%-7.87%. For high-speed objectives, dual path single-transistor-clocked...
As the devices are scaling down, combinational logic will become susceptible to soft errors. The conventional error tolerant methods for errors on do not provide enough high capability with reasonably small performance penalty. This paper investigates feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits tolerance. We analyze behavior null convention (NCL) in presence particle strikes, and propose an pipeline soft-error correction a novel technique improve robustness...
2D metal halides have attracted increasing research attention in recent years; however, it is still challenging to synthesize them via liquid-phase methods. Here demonstrated that a droplet method simple and efficient for the synthesis of multiclass halides, including trivalent (BiI3 , SbI3 ), divalent (SnI2 GeI2 monovalent (CuI) ones. In particular, first experimentally achieved, which thinnest thickness ≈6 nm. The nucleation growth these halide nanosheets are mainly determined by...
Deep Learning (DL) offers the advantages of high accuracy performance at tasks such as image recognition, learning complex intelligent behaviors, and large-scale information retrieval problems web search. To attain benefits DL, computational energy-consumption demands imposed by underlying processing, interconnect, memory devices on which software-based DL executes can benefit substantially from innovative hardware implementations. Logic-in-Memory (LIM) architectures offer potential...
Ultrathin hybrid perovskites, with exotic properties and two-dimensional geometry, exhibit great potential in nanoscale optical optoelectronic devices. However, it is still challenging for them to be compatible high-resolution patterning technology toward miniaturization integration applications, as they can readily damaged by the organic solvents used standard lithography processes. Here, a flexible three-step method developed make multicolor on perovskite, particularly achieved single...
As the devices are scaling down, combinational logic will become susceptible to soft errors. The conventional error tolerant methods for errors on do not provide enough high capability with reasonably small performance penalty. This paper investigates feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits tolerance. We analyze behavior Null Convention Logic in presence particle strikes, and propose a novel technique improve robustness threshold gates, which basic...
Domino circuits are used to achieve higher system performance than static CMOS techniques. This work briefly surveys domino keeper designs for high fan-in circuits. A new circuit structure is shown in this paper that reduces the power-delay-product over 16% as compared previous techniques with keepers
Low power design can be exploited at various levels, e.g., system level, architecture circuit and device level. This paper gives a brief overview of low principals, then focuses discussion on level methods specifically state-of-the-art techniques clocking systems. Finally we discuss optimization