This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay designed on these illustrate a range of important functions necessary for the implementation integrated VLSI systems and lend insight into circuit design techniques optimized physical properties devices. To explore hybrid electro-mechanical model relays' electrical mechanical characteristics has been developed, correlated to measurements, then also applied...

Power density has grown to be the dominant challenge for continued complementary metal–oxide–semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process technology, this led renewed interest mechanical computing ultralow-power integrated circuit (IC) applications. This paper provides a brief history of followed by an overview various types micromechanical switches, particular emphasis on electromechanical relays since they are among most...

A 4-terminal (4T) relay technology is proposed for complementary logic circuit applications. The advantage of the 4T design that it provides a means electrically adjusting switching voltage; as result, can mimic operation either an n-channel or p-channel MOSFET. Fabricated relays exhibit good on-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> > 700 ¿A V xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 1 V) and zero...

Micro-electro-mechanical (MEM) relays recently have been proposed for ultra-low-power digital logic applications because their ideal switching behavior can potentially allow the supply voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> ) to be scaled down further than CMOS devices [1–3]. This paper describes design techniques achieve reliable (high-endurance) MEM relay operation. Prototype fabricated using a CMOS-compatible...

A testchip demonstrates monolithic integration of micro-electro-mechanical (MEM) switch circuit building blocks for logic, timing, I/O and memory functions. Experimental results show functionality an inverter, XOR, carry-generation block, oscillator, DAC, latch, 10-cell DRAM.

The impact of device operating parameters on the ON-state resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) microelectromechanical relays with tungsten (W) electrodes is reported. Due to susceptibility W oxidation, increases undesirably over cycles. This issue aggravated by Joule heating when relay in state. experimental results confirm that shorter ON time, as well off...

We investigate surface-enhanced Raman scattering (SERS) from gold-coated silicon-germanium nanocone substrates that are decorated with 30-nm spherical gold nanoparticles (AuNPs). Finite-element simulations suggest individual nanocones generate stronger electromagnetic enhancement axial polarization (i.e., parallel to the vertical axis of nanocones) than transverse in plane substrate), whereas excitation a typical microscope is mainly polarized plane. introduce practical approach improve SERS...

A dual-ended (¿seesaw¿) relay design is proposed for ultralow-power digital logic applications. Fabricated seesaw relays demonstrate a perfectly complementary switching behavior that symmetric about <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> /2, with extremely steep (< 0.1 mV/dec) and low on -state resistance 1 k¿). The operation provides maximum operating voltage margin minimal...

Various logic functions can be implemented by appropriately biasing a single seesaw relay. The relay also configured as bistable latch so that memory cell with one and access transistor. Measurements of switching speed are well matched to lumped-parameter modeling results. <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hfill$</tex></formula> [2009-0267]

This paper describes the micro-architecture and circuit techniques for building multipliers with micro-electromechanical (MEM) relays. By optimizing circuits to suit relay device characteristics, performance of based multiplier is improved by a factor ~8× over any known static CMOS-style implementation, ~4× CMOS pass-gate equivalent implementations. A 16-bit shown offer ~10× lower energy per operation at sub-10 MOPS throughputs when compared an optimized 90 nm technology node. To demonstrate...

Power density has grown to be the dominant challenge for continued IC technology scaling. This led renewed interest in mechanical computing ultra-low-power applications. paper provides an overview of recent developments electrostatic micro-relay design and process technology, discusses scaling achieve MEM switches that are advantageous over CMOS transistors digital logic

Contact adhesive force (Fa) scaling is critical for relay miniaturization, since the actuation area and/or voltage must be sufficiently large to overcome spring restoring (Fk) in order turn on and Fk larger than Fa off relay. In this work, contact investigated MEM logic relays with dimple regions as small 100 nm lateral dimension. The results indicate that van der Waals predominant. An of 0.02 nN/nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, quantifies the further benefits scaled relay designs. Finally, we demonstrate chip successfully power-gating...

Four-terminal-relay inverter circuit characteristics are investigated. To achieve maximum noise margin and zero crowbar current while allowing for relay-to-relay variations, the optimal biasing scheme provides switching that is symmetric about V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> /2 with minimum hysteresis no possibility of both pull-down pull-up devices being on simultaneously.

Multiple-input relays are proposed to enable more compact implementation of digital logic circuits, and the first functional prototypes presented. A relay with three equally sized input electrodes is demonstrated perform various three-input functions, a delay that can be well predicted by lumped-parameter model. Relays differently used complex functions. flash-type analog-to-digital converter presented as one example.

Previously reported electrostatically actuated four-terminal (4T) relays suffer from a relatively weak body bias effect and undesirable influence of source/drain voltages on gate switching voltages. In this letter, an improved 4T relay design is demonstrated to resolve these issues.

An electromechanical diode nonvolatile memory cell design is proposed for implementation of compact (4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) cross-point arrays. The first prototype cells are demonstrated to operate with relatively low set/reset voltages and excellent retention characteristics multi-time programmable (with endurance exceeding 10 xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cycles).

Multi-functional digital logic circuits, each utilizing only two relays, are demonstrated for the first time. This work can be extended to relay designs comprising greater than input electrodes and/or sets of source/drain electrodes, more compact realization zero-leakage ICs in future.

As state of the art flash memory technologies scale down to sub 30 nm node, conventional floating gate approaches its physical scaling limit mainly because high coupling ratio (GCR) requirement secure proper window. Here, we report a novel device called Cr metal thin film (MTFM) that can circumvent GCR issue and extend scalability by employing as storage layer. devices with simple low temperature processes produced wide window 10 V at ±18 voltage sweep only 0.3. Such large be adopted for...

50-mV operation of digital integrated circuits at room temperature is demonstrated for the first time using body-biased microelectromechanical relays. An improved relay design and self-assembled molecular coating provide lower contact adhesion to reduce hysteretic switching behavior, so that relays operate reliably with sub-50-mV gate voltage swing ultra-low active power consumption as well zero static consumption.

This paper presents the development of electrostatically actuated polymer-based microelectromechanical relays as a potential replacement for organic field-effect thin-film transistors in order to enable near-zero-power flexible transparent large-area electronics. A low-temperature five-mask surface-micromachining process is developed fabricate two types prototype relays: purely polymeric and partially (inorganic-organic hybrid) relays. Experimental results demonstrate operation prototypes...

A relatively thin structural film with low strain gradient is developed for micro-relay technology. Relays fabricated using this as the material operate pull-in voltage and hysteresis, which desirable achieving low-power high-endurance relay integrated circuits. With improved film, relays scaled layout dimensions are demonstrated first time.

Micromachined polymer-based cantilever probes have been proposed for atomic force microscopes (AFMs) in order to enable noninvasive, rapid high-resolution topography imaging and mechanical measurements of live biological samples. Polymer-based developed date still consist a rather stiff with relatively high spring constant prone causing deformation and/or distortion sample surfaces during scanning blunt tip that limits imaging. This paper reports the design, fabrication, characterization...

A high-fill factor micro-mirror for two-axis operation has been designed, analyzed, and fabricated by using electroplated copper thick photoresist sacrificial mold. The mirror crossbar springs under the plate in order to achieve a factor. maximum actuation angle before pull-in device measured as 2.65/spl deg/ at 244 V. This shows good agreement with analysis simulation results. radius of curvature RMS surface roughness have 3.8 cm 12 nm, respectively.

A low-thermal-budget (CMOS-compatible) process for microshell encapsulation of MEMS devices is proposed. Inkjet-printing silver (Ag) nanoparticle ink demonstrated to form porous microshells through which sacrificial oxide (SiO2) can be selectively removed release structures. second inkjet printing using finer gold (Au) effectively seal the microshells. The mechanical strength a printed (~3 μm thick) sufficient encapsulating regions greater than 1 mm in length.