This paper presents the development of a wake-up receiver (WuRX) at nanowatt power levels for event-driven applications. improves state art, obtaining higher sensitivity than previous work in 151.8- and 433-bands, low-power operation, robustness to interference due an integrated offset compensation algorithm operating without any external calibration. Simultaneous operation high are achieved through passive detector design based upon terminal impedance boundary condition-based optimization...

Event-driven sensor nodes have applications in agriculture, infrastructure, and perimeter monitoring are characterized by spending the vast majority of their time an asleep-yet-alert state. In this state, node must wake to incoming RF wakeup commands from antenna with minimal dc power, as total percentage power sleep mode dominates if events sufficiently infrequent. The receiver (WuRX) is one critical block node's It maximize sensitivity consumptions 10nW or less battery lifetime even enable...

Analog/mixed-signal (AMS) computation can be more energy efficient than digital approaches for deep learning inference, but incurs an accuracy penalty from precision loss. Prior AMS focus on small networks/datasets, which maintain even with 2b precision. We analyze applicability of to larger networks by proposing a generic error model, implementing it in existing training framework, and investigating its effect ImageNet classification ResNet-50. demonstrate significant recovery exposing the...

Improving system lifetime and robustness is a key to advancing self-powered platforms for real world applications. A complete self-powered, battery-less, wearable platform requires microwatt-power system-on-chip (SoC), operating reliably within this budget, capable of surviving long periods without charging, recovering from power loss its previous state. To meet these requirements, we designed wireless sensing heterogeneous system-in-package (SiP) containing an ultra-low (ULP) SoC,...

This paper presents a 1.05 MHz, on-chip RC relaxation oscillator (ROSC) with temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation 100 ppm over the body-compatible range 0-40°C. The TC increases to 4.3 from -15 °C 55 °C. high stability is achieved using PTAT current reference TC-tunable resistor bank for first-order frequency error compensation along digital (DFC) block single-bit sensor second-order compensation. A measured RMS period jitter 160 ps high-speed comparator....

This letter presents an RISC-V microprocessor implemented using a proposed scalable dynamic leakage suppression (SDLS) logic style. Together with custom adaptive clock generator and voltage scaling controller, the SDLS realizes fully integrated modified frequency (DVFS) scheme that enables nW-level performance flexibility for battery-less IoT sensing nodes in energy-scarce environments. At nominal core VDD of 0.6 V, can scale its from 6 nW at 11-Hz operating to 140 8.2-kHz frequency. Across...

A 507nW self-powered SoC is demonstrated for ultra-low power (ULP) internet-of-things (IoT) applications. The includes ULP system-in-package (SiP) interfaces that enable its harmonious integration with a radio transmitter (TX) and non-volatile memory (NVM). energy harvesting platform manager (EH-PPM) powers the as well off-chip components optimized low quiescent power. It supplies 0.5V, 1.0V, 1.8V can also sensors SiP while running an example shipping-integrity tracking algorithm. monitor...

To achieve the exponential growth needed for a 1-trillion-node Internet of Things (IoT) in next decade, innovative solutions are required to eliminate recurring battery replacement costs, enable reliable operation environments with uncontrolled temperatures, and leverage massive communication infrastructure at multi-GHz frequency bands. Sub-100nW ultra-low-power (ULP) wakeup receivers (WuRx's) promise energy-efficient event-driven applications [1]-[3], but can be susceptible temperature...

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise low-power circuit design methodologies aggressive voltage scaling to satisfy both the low consumption input-referred noise requirements of ECG acquisition systems. was realized with three-stage fully differential AC-coupled amplifier, it provides bio-signal programmable gain bandwidth. implemented in 130 nm CMOS process, has measured...

This work presents a 33 nW wake-up receiver with -106 dBm sensitivity at 428 MHz. Within-bit duty cycling allows RF gain nano-watt DC power levels providing 26 dB improvement over prior art iso-power. An MEMS filter and an automatic offset control loop suppress noise reject interference. The can be digitally tuned across power, latency, to provide flexible functionality from indoor short range outdoor long-range applications.

This article presents the first demonstration of a sub-100 nW CMOS wakeup receiver (WuRx) with envelope detector (ED)-first architecture that operates at multigigahertz frequencies. The 2.2 GHz S-band WuRx can operate in two modes show tradeoff between power consumption and RF sensitivity. In low-power mode, consumes 11.3 achieves an sensitivity -65 dBm. high-sensitivity 28.2 -68 Measurement results indicate is robust to continuous-wave in-band interferers, as large -20 dB...

This letter presents a reconfigurable wake-up receiver, which obtains -106-dBm sensitivity with power consumption as low 33 nW. Bit-level duty cycling provides 68-dB RF gain at sub-$\mu \text{W}$ average consumption, improving over other receivers. The receiver rejects interference using compact MEMS filter and fully automatic offset control loop. Digital tuning of dc power, latency, high levels flexibility to enable wide variety applications, spanning latency from 240 ms 5 s, 288 nW nW,...

In order to solve the problem of actuator failure flexible joint manipulator, adaptive fault-tolerant control for a manipulator with bounded disturbance is proposed, both partial and stuck are considered. The lows devised by means dynamic surface technique, compensated via design robust items. stability system guaranteed Lyapunov method. effectiveness theoretical schemes finally verified two simulation examples.

This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the maximize energy/power...

This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (VT) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the maximize energy/power saving. A test chip implements a 1Kb 6T SRAM, FIR filter, 51-stage RO showcase how works circuit...

This brief presents a multicore embedded processor with reconfigurable same-instruction multiple process (RSIMP) architecture design to reduce the power consumption of instruction memory (IM), thus reducing total processor. RSIMP is applied scenario in which several cores (each representing coarse-grained process) execute highly identical sequence parallel. They are then reconfigured master-slave mode only master core fetches instructions and distributes slave core(s), whereas IM shut down...

Register files (RFs) consume significant power in low-power processors, and their specifications vary substantially for different applications. Challenges exist identifying the appropriate RF design optimizing RFs specifications. This paper not only explores methodologies of designing low high performance it also extends a virtual prototyping (ViPro) tool to support fast efficient estimation knobs on overall multi-port macros. To enable aggressive exploration design, three bitline (BL)...

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists canary-based V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> tracking is presented. 337X 4.3X power reductions are achieved multiple tracking, respectively; combining both saves 1444X in active 12.4X leakage at the 0.38V.

A novel method for SRAM cell standby leakage measurement is presented, which enables accurate testing and decoupling of sub-threshold (I_sub), gate (I_gate) junction (I_junc) in each transistor. Moreover, the array based technique can not only precisely measure small current but also compensate impact from random variations. The front-end layout kept original to preserve actual physical environment. verified SMIC 65nm technology. data I_sub, I_gate I_junc pull-down (PD), pull-up (PU)...

This work presents a 1.05 MHz on-chip RC relaxation oscillator (ROSC) design with temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation 100 ppm over the body-compatible range 0 to 40°C (the TC increases 4.3 from -15 55°C). The high stability is achieved using PTAT current reference TC-tunable resistor bank for first-order frequency error compensation along digital (DFC) block single-bit sensor second-order compensation. A measured RMS period jitter 160 ps high-speed...

Adaptive VSS boosting with process variation compensation is proposed to reduce the standby leakage by 6X at room temperature and improves write static noise margin. The N-pulse read assist circuit enables higher stability faster speed. systematic BL capacitance detected, a proper WL voltage generated mitigate discharging speed 20%.

A high performance bulk floating body memory device is demonstrated in this work. Experimental results show a data retention of 1.89s and initial window over 60μA@85°C, which are excellent features for eDRAM application. novel read method based on parasitic BJT effect introduced to improve performance. The impact process parameters investigated P well doping found be the key factor. scaling potential proposed scheme also evaluated by measurement devices with several (W/L, T <sub...