A5052796636- Food composition and properties
- Parallel Computing and Optimization Techniques
- Microbial Metabolites in Food Biotechnology
- Food Quality and Safety Studies
- Interconnection Networks and Systems
- Polysaccharides Composition and Applications
- Advanced Data Storage Technologies
- Reproductive Biology and Fertility
- Distributed systems and fault tolerance
- Target Tracking and Data Fusion in Sensor Networks
- Fuzzy Logic and Control Systems
- Proteins in Food Systems
- Genomics, phytochemicals, and oxidative stress
- Distributed and Parallel Computing Systems
- Neural Networks and Applications
- Nutrition, Health and Food Behavior
- Analytical Chemistry and Chromatography
- Essential Oils and Antimicrobial Activity
- Cloud Computing and Resource Management
- Phytoestrogen effects and research
- Antibiotics Pharmacokinetics and Efficacy
- Ovarian cancer diagnosis and treatment
- Face and Expression Recognition
- Phytase and its Applications
- Image and Video Stabilization
Wonkwang University
2016-2025
Kyung Hee University
2021-2023
Korea University
1990-2019
Seoul National University
2002-2015
Iowa State University
2013-2015
Seoul National University Hospital
2014
Dongyang Mirae University
2013
University of Illinois Chicago
2013
Intel (United States)
2011-2012
Hanyang University
2001-2011
Due to their massive computational power, graphics processing units (GPUs) have become a popular platform for executing general purpose parallel applications. GPU programming models allow the programmer create thousands of threads, each same computing kernel. GPUs exploit this parallelism in two ways. First, threads are grouped into fixed-size SIMD batches known as warps, and second, many such warps concurrently executed on single core. Despite these techniques, resources cores still...
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources the memory subsystem. If resource sharing is unfair, some applications can be delayed significantly while others are unfairly prioritized. Previous research proposed separate fairness mechanisms each individual resource. Such resource-based implemented independently make contradictory decisions, leading to low and loss of performance. Therefore, coordinated mechanism that provides entire shared desirable. This...
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers different cores on a chip multiprocessor (CMP) can cause interference with prefetch and demand accesses other cores. Because existing prefetcher throttling techniques do not address this prefetcher-caused inter-core interference, aggressive systems lead to performance degradation wasted bandwidth consumption.
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources the memory subsystem. If resource sharing is unfair, some applications can be delayed significantly while others are unfairly prioritized. Previous research proposed separate fairness mechanisms each individual resource. Such resource-based implemented independently make contradictory decisions, leading to low and loss of performance. Therefore, coordinated mechanism that provides entire shared desirable.
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some treat requests the same as demand requests, others always prioritize over However, none of these rigid result in best performance because they do not take into account usefulness If are useless, treating prefetches demands equally can lead to significant loss extra bandwidth consumption. In contrast, if useful, prioritizing hurt by reducing throughput delaying...
A primary use of chip-multiprocessor (CMP) systems is to speed up a single application by exploiting thread-level parallelism. In such systems, threads may slow each other down issuing memory requests that interfere in the shared subsystem. This inter-thread system interference can significantly degrade parallel performance. Better request scheduling mitigate performance degradation. However, previously proposed algorithms for CMPs are designed multi-programmed workloads where core runs an...
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management these shared resources; however, none them take into account prefetch requests. Without prefetching, significant performance is lost, which why existing systems prefetch. By not taking requests, recent shared-resource often significantly degrade both fairness, rather than improve in presence prefetching.
DRAM systems achieve high performance when all banks are busy servicing useful memory requests. The degree to which is called Bank-Level Parallelism (BLP). This paper proposes two new cost-effective mechanisms maximize BLP. BLP-Aware Prefetch Issue (BAPI) issues prefetches into the on-chip Miss Status Holding Registers (MSHRs) associated with each core in a multi-core system such that requests can be serviced parallel different banks. BLP-Preserving Multi-core Request (BPMRI) does actual...
Indirect branches have become increasingly common in modular programs written modern object-oriented languages and virtual machine based runtime systems. Unfortunately, the prediction accuracy of indirect has not improved as much that conditional branches. Furthermore, previously proposed branch predictors usually require a significant amount extra hardware storage complexity, which makes them less attractive to implement.