Spike-timing-dependent plasticity (STDP) is a popular approach for online learning that determines synaptic weight updates based on the relative timing of temporal events pre-synaptic and post-synaptic spikes. Online very effective fast low power processing locally sensed signals. Moreover, memristor (or "memory resistor") has garnered attention as key component in emerging circuits, due large part to inherent device. Circuits leverage metal-oxide memristors, including HfO <inf...

Memristors are a suitable candidate to design synapse circuits and neuromorphic systems. Due device voltage variability, operating memristive with reliability is big challenge. To enhance the of synapse, RESET failure needs be considered. In this work, we focused on modeling variation. Here, defined as hard due high being applied. The proposed Verilog-A model derived based experimental data collected from 1T1R devices, which fabricated 65 nm CMOS process. system-level simulation, will...

Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable the commonly used voltage-pulse-based programming approaches require precisely shaped pulses avoid failure. In this paper, we demonstrate current-limiting-based that provides more predictable analog memory behavior when reading writing memristive synapses. With our proposed design READ current can be optimized by about...

The synapse is a key element of neuromorphic computing in terms efficiency and accuracy. In this paper, an optimized current-controlled memristive circuit proposed. Our proposed demonstrates reliability the face process variation inherent stochastic behavior memristors. Up to 82% energy optimization can be seen during SET operation over prior work. addition, READ shows up 54% savings. approach also provides more reliable programming traditional methods. This design demonstrated with 4-bit...

Abstract In neuromorphic computing, different learning mechanisms are being widely adopted to improve the performance of a specific application. Among these techniques, spike-timing-dependent plasticity (STDP) stands out as one most favored. STDP is simply managed by temporal information an event, which biologically inspired. However, prior works on focused circuit implementation or software simulation for evaluation. Previous also lack comparative analysis performances implementations. This...

Short-term plasticity (STP) is a synaptic modification process found in biological synapses that increases the computational power of neuronal network. To implement rules, we use memristor-based synapse due to its inherent plasticity. The designed operate low resistance state (LRS) region using current-controlled mechanism account for device non-idealities encountered at high (HRS). In this work, mixed-signal STP circuit design. uses digital part generate pulses initiate weight change, and...

Neuromorphic computing systems have emerged as powerful computation tools in the field of object recognition and control systems. However, training these systems, which are usually characterized by recurrent connectivity, requires abundant computational resources: memory, computation, data, time. Reservoir (RC) framework reduces this high cost focusing effort on only a small subset connections thus allowing to be amenable hardware implementation. Using memristors construct reservoir...

In this paper, in an effort to implement unsupervised learning algorithm for silicon neurons, we present a mixed-signal Leaky Integrate-And-Fire (LIF) neuron with two different integrated homeostasis circuits using programmable leak. The mechanism is realized by controlling the charge accumulation rate on integrator varying leakage external signals. proposed have been simulated 65nm CMOS process and their performances compared existing implementations. Results show that our designs achieve...

Abstract The synapse is a key element circuit in any memristor-based neuromorphic computing system. A memristor two-terminal analog memory device. Memristive synapses suffer from various challenges including high voltage, SET or RESET failure, and READ margin issues that can degrade the distinguishability of stored weights. Enhancing resolution very important to improving reliability memristive synapses. Usually, small for with 4-bit data precision. This work considers step-by-step analysis...

The big video data size today imposes huge pressure on storage. variation and aging induced memory failures significantly influence the output quality. Recently, researchers have developed different designs for videos, deep learning, other data-intensive applications, which enables better energy-quality tradeoffs with design constraints. Unfortunately, designing has been proven to be a very challenging problem due to: 1) various constraints; 2) multiple bitcell options; 3) layout integration...

Spike-timing-dependent plasticity (STDP) is a widely used technique for online learning that updates synapse weights based on the timing of pre- and post-synaptic spikes. Metal-oxide memristors, including HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , are promising in emerging synaptic circuits due to their inherent plasticity, but non-idealities must be carefully considered design process. In this paper, current-controlled...

To create hardware platforms that are compact, power-efficient, and suitable for online learning, we develop a spike-driven synaptic plasticity (SDSP) circuit Hafnium-Oxide-based memristive neuromorphic core. The core includes configurable integrate-and-fire (IAF) neuron current-controlled synapse, with SDSP modifying weights based on pre-synaptic spikes, the post-synaptic neuron's membrane potential, recent spiking activity. Compared to widely used spike-timing-dependent (STDP), model can...

With the advent of Internet Things (IoT) technologies and availability a large amount data, deep learning has been applied in variety artificial intelligence (AI) applications. However, sharing personal data using IoT edge devices carries inherent risks to individual privacy. Meanwhile, energy memory resources needed during inference process become constraint resource-limited devices. This article brings hardware optimization meet tight power budget by considering privacy, accuracy,...

Neuromorphic computing is a leading option for non von-Neumann architectures. With it, neural networks are developed that derive architectural inspiration from how the brain operates with neurons, synapses, and spikes. These often implemented in either software or hardware based neuroprocessors designed to handle specific tasks efficiently. Even if hardware, emulation instrumental determining worthwhile features capabilities of architecture. In this work two novel introduced: software-based...

The synapses are fundamental components of spiking neural networks (SNNs). Although metal-oxide memristors, including Hafnium-Oxide (Hf0 <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ), offer potential in synaptic circuits, the design process must account for their non-idealities. This paper proposes a current-controlled memristive synapse with limited range operation close to low resistance state (LRS) address device non-idealities...

A key issue in the field of neuromorphic computing is how much inspiration to take from brain im-plementation hardware systems. For example, neuron implementations have varied non-spiking McCulloch-Pitts style neurons extremely biologically-detailed Hodgkin Huxley neurons. In this work, we examine a variety biologically-inspired features include models for We evaluate such as leak, absolute refractory period, and relative period. these terms their impact on algorithm application performance.

In this article, a flexible power-efficient video memory is presented that can dynamically adjust the strength of error correction code (ECC), thereby enabling power-quality tradeoff based on application requirements. Specifically, we utilize bit significance characteristics data to develop low-cost parity storage scheme supports both hamming code-74 (ECC74) and code-1511 (ECC1511). Based this, propose with three dynamic adaptation schemes (i.e., ECC74, ECC1511, no ECC) meet different Our...

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists two logic transistors implemented generic triple-well CMOS process. key idea is use parasitic junction capacitance built between common cell-body and storage node. For each write access, voltage transition on couples up levels. technique enhances read performance without using additional cell devices. also provides much strong immunity from...

The demand for mobile video streams is constantly increasing. With this comes a need devices to receive more videos at ever increasing quality. However, due the large size of data and intensive computational requirements, streaming requires frequent memory access that consume substantial amount device power; as result, battery life limited. In paper, we present content-adaptable Region-of-Interest (ROI)-aware storage technique promotes power savings. During encoding process on transmitting...