This paper proposes an architecture to develop machine learning/deep learning models for anomaly network intrusion detection systems on reconfigurable computing platforms. We build two validate the framework: Anomaly Detection Autoencoder (ADA) and Artificial Neural Classification (ANC) in NetFPGA-sume platform. Three published data sets NSL-KDD, UNSW-NB15, CIC-IDS2017 are used test deployed models’ throughput, latency, accuracy. Experimental results with NetFPGA-SUME show that ADA model...

This study proposes a heterogeneous hardware-based framework for network intrusion detection using lightweight artificial neural models. With the increase in volume of exchanged data, IoT networks’ security has become crucial issue. Anomaly-based systems (IDS) machine learning have recently gained increased popularity due to their generation’s ability detect unseen attacks. However, deployment anomaly-based AI-assisted IDS devices is computationally expensive. A high-performance and...

Summary Over the last decades, Bioinformatics has been being in its honeymoon phase with more and new algorithms as well their improvements proposed. In Bioinformatics, sequence alignment step is considered an integral part that directly contributes to DNA, RNA, or protein identifications. Despite undeniable enhancements from provided computing architectures recent years, it still far state already achieved ideal performance. this work, we focus on one of most perfect justifiable steps a...

In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays essential role in many security applications, such as transport layer (TLS), internet protocol (IPsec), wireless sensor networks (WSNs). The proposed designs of hardware implementation only focus on a single variant use resources. These proposals cannot be used for resource-constrained applications or the devices that need provide...

The communication infrastructure is one of the important components a multicore system along with computing cores and memories. A good interconnect design plays key role in improving performance such systems. In this paper, we introduce hybrid using both standard bus our area-efficient delay-optimized network on chip for heterogeneous systems, especially hardware accelerator An adaptive data communication-based mapping reconfigurable accelerators proposed to obtain low overhead latency...

High-level synthesis (HLS) is an automated design process that deals with the generation of behavioral hardware descriptions from high-level algorithmic specifications. The main benefit this approach ever-increasing system-on-chip (SoC) complexity and ever-shorter time-to-market can still be both manageable achievable. This advantage, coupled increasing number available heterogeneous platforms loosely couple general-purpose processors Field Programmable Gate Array-based co-processors, led to...

This paper proposes an FPGA-based multicore architecture to integrate multiple DDoS defense mechanisms for protection. The allows cooperating mitigation techniques classify incoming network packets. proposed consists of two separate partitions static and dynamic. partition includes packet pre-processing post-processing modules while the filtering are implemented within dynamic partition. These can be by either hardware custom computing cores or general purpose soft processors both. In all...

With the rising data evolution, demand for secured communications over networks is immensely. Elliptic Curve Cryptography (ECC) provides an attractive solution to fulfill requirements of modern network applications. Many proposals published year different variants ECC satisfied some issues. Nevertheless, applications such as Internet-of-Thing (IoT) and Software-Defined Networking (SDN) put on various aspects can only be solved by algorithms. Looking at this point view, efficient architecture...

The smart environmental management system proposed in this work offers a new approach to monitoring by utilizing data from IoT stations and MODIS satellite imagery. is designed be deployed vast regions, such as the Mekong Delta, with low building operating costs, making it cost-effective solution for monitoring. leverages telemetry collected combination MOD09GA, MOD11A1, MCD19A2 daily image products develop computational models that calculate values land surface temperature (LST), 2.5 10...

In recent years, Internet of Thing (IoT) applications with video processing deployed on edge computing platforms have been widely exploited for many areas, such as surveillance, object monitoring, or checkin/check-out systems.While H.264 format is used most modern cameras due to its efficiency, the power usually needs be higher process videos in acceptable intervals.This paper proposes an approach based high-level synthesis technique accelerate encoding by Field Programmable Gate Array...

Asynchronous circuits are more and predominant because their advantages in comparison with synchronous circuits. While asynchronous can be implemented custom VLSI, fabricated-time is too long to allow rapid prototyping. Meanwhile, FPGA devices dominant implementation media for digital Unfortunately, they do not support of the lack circuit elements such as Muller gates, etc. This paper proposes a new efficient technique build hazard-free gates on Xilinx FPGA. Timing and/or area constraints...

In this paper, we present an overview of interconnect solutions for hardware accelerator systems. A number are presented: bus-based, DMA, crossbar, NoC, as well combinations these. The paper proposes analytical models to predict the performance these and implements them in practice. jpeg decoder application is implemented our case study different scenarios using presented solutions. We profile extract input data model. Measurement results show that NoC solution combined with a bus-based...

FPGA device is a dominant implementation medium for digital circuits. Unfortunately, they do not support asynchronous circuits because of the lack circuit elements such as Muller gates, etc. In this paper, new efficient approaches are proposed to prototype or mixed synchronous/ on look-up table-based (LUT) rapidly. The developed techniques based building which play an important role in hazard-free predefined libraries HDL and EDIF format. Timing and/or area constraints place&route tool...

The development of machine learning has made a revolution in various applications such as object detection, image/video recognition, and semantic segmentation. Neural networks, class learning, play crucial role this process because their remarkable improvement over traditional algorithms. However, neural networks are now going deeper cost significant amount computation operations. Therefore they usually work ineffectively edge devices that have limited resources low performance. In paper, we...

With the very fast improvements in technology, amount of data DNA alignment is exponential growth. Although there are more and new algorithms proposed last decade to increase mapping performance, it still takes up many days for aligning whole human genome even with large clusters. In this work, we focus on one most time-consuming steps state-of-the-art algorithm, seed extension BWA-MEM algorithm. We propose an FPGA-based IP core phase algorithm so that FPGA can be used accelerate overall...

Multicore processing, especially heterogeneous multicore, is being increasingly used for data intensive processing in embedded systems. An important challenge multicore is, efficiently, to get the computing core that needs it. In order have an efficient interconnect design architectures, a detailed profiling of communication patterns necessary. this work, we propose heuristic-based approach application-specific custom using quantitative information. The ultimate goal automatically, most...

As one of the main types Distributed Denial Service (DDoS) attacks, SYN flood attacks have caused serious issues for servers when legitimate clients may be denied connections. There is an essential demand a sufficient approach to mitigate attacks. In this paper, we introduce efficient high-throughput and low-latency defender architecture, carefully designed with pipeline model. A mathematical model also introduced architecture estimating protection throughput latency. The first prototype...

SHA-256 is a well-known algorithm widely used in many security applications. The provides sufficient level of safety and can be performed efficiently by FPGA devices due to its high parallelism level. This paper presents high-throughput, low hardware resources usage, power-efficiency architecture the targeting FPGA-based embedded platforms. computing core takes advantage specific achieve performance. We implement with description languages so that technology-independent. Therefore, suitable...